/* set arbiter mode */
int dram_host_port_arbiter_mode_set(unsigned int mode)
{
HostMbagcReg = DRAM_MBAGCR;
SHOW_HOST_CFG_REG(HostMbagcReg);
HostMbagcReg->Mode = mode;
return 0;
}
/* get arbiter mode */
int dram_host_port_arbiter_mode_get(void)
{
HostMbagcReg = DRAM_MBAGCR;
SHOW_HOST_CFG_REG(HostMbagcReg);
return HostMbagcReg->Mode;
}
/* disable access according to port */
int dram_host_port_acs_disable(__dram_host_port_e port)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
HostCfgReg->AcsEn = 0;
return 0;
}
/* set command number according to port */
int dram_host_port_cmd_num_set(__dram_host_port_e port, unsigned int num)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
HostCfgReg->CmdNum = num;
return 0;
}
/* set priority level according to port */
int dram_host_port_prio_level_set(__dram_host_port_e port, unsigned int level)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
HostCfgReg->PrioLevel = level;
return 0;
}
/* set wait state according to port */
int dram_host_port_wait_state_set(__dram_host_port_e port, unsigned int state)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
HostCfgReg->WaitState = state;
return 0;
}
/* get access number according to port */
int dram_host_port_acs_num_get(enum dram_host_port port)
{
int ser = id_serial[port].serial;
int type = host_port_type_target(port);
if (type == DRAM_TYPE_RM)
HostCfgReg = DRAM_RMCR_PORT(ser);
else if (type == DRAM_TYPE_MM)
HostCfgReg = DRAM_MMCR_PORT(ser);
else if (type == DRAM_TYPE_MBA)
HostCfgReg = DRAM_MBACR_PORT(ser);
SHOW_HOST_CFG_REG(HostCfgReg);
return HostCfgReg->AcsNum;
}
/* set priority threshold according to port */
int dram_host_port_prio_threshold_set(enum dram_host_port port, unsigned int level)
{
int ser = id_serial[port].serial;
int type = host_port_type_target(port);
if (type == DRAM_TYPE_RM)
HostCfgReg = DRAM_RMCR_PORT(ser);
else if (type == DRAM_TYPE_MM)
HostCfgReg = DRAM_MMCR_PORT(ser);
else if (type == DRAM_TYPE_MBA)
HostCfgReg = DRAM_MBACR_PORT(ser);
SHOW_HOST_CFG_REG(HostCfgReg);
HostCfgReg->PrioThreshold = level;
return 0;
}
/* set wait state according to port */
int dram_host_port_wait_state_set(enum dram_host_port port, unsigned int state)
{
int ser = id_serial[port].serial;
int type = host_port_type_target(port);
if (type == DRAM_TYPE_RM)
HostCfgReg = DRAM_RMCR_PORT(ser);
else if (type == DRAM_TYPE_MM)
HostCfgReg = DRAM_MMCR_PORT(ser);
else if (type == DRAM_TYPE_MBA)
HostCfgReg = DRAM_MBACR_PORT(ser);
SHOW_HOST_CFG_REG(HostCfgReg);
HostCfgReg->WaitState = state;
return 0;
}
/* get command number according to port */
int dram_host_port_cmd_num_get(__dram_host_port_e port)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
return HostCfgReg->CmdNum;
}
/* get access state according to port */
int dram_host_port_acs_get(__dram_host_port_e port)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
return HostCfgReg->AcsEn;
}
/* get priority level according to port */
int dram_host_port_prio_level_get(__dram_host_port_e port)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
return HostCfgReg->PrioLevel;
}
/* get wait state according to port */
int dram_host_port_wait_state_get(__dram_host_port_e port)
{
HostCfgReg = DRAM_HOST_CFG_PORT;
SHOW_HOST_CFG_REG(HostCfgReg);
return HostCfgReg->WaitState;
}
