static void sa1100_int(int irq, void *dev_id, struct pt_regs *regs)
{
struct uart_info *info = dev_id;
struct uart_port *port = info->port;
unsigned int status, pass_counter = 0;
status = UART_GET_UTSR0(port);
status &= (SM_TO_UTSR0(port->read_status_mask) | ~UTSR0_TFS);
do {
if (status & (UTSR0_RFS | UTSR0_RID)) {
/* Clear the receiver idle bit, if set */
if (status & UTSR0_RID)
UART_PUT_UTSR0(port, UTSR0_RID);
sa1100_rx_chars(info, regs);
}
/* Clear the relevent break bits */
if (status & (UTSR0_RBB | UTSR0_REB))
UART_PUT_UTSR0(port, status & (UTSR0_RBB | UTSR0_REB));
if (status & UTSR0_RBB)
port->icount.brk++;
if (status & UTSR0_REB) {
#ifdef SUPPORT_SYSRQ
if (port->line == sa1100_console.index &&
!info->sysrq) {
info->sysrq = jiffies + HZ*5;
}
#endif
}
if (status & UTSR0_TFS)
sa1100_tx_chars(info);
if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
break;
status = UART_GET_UTSR0(port);
status &= (SM_TO_UTSR0(port->read_status_mask) | ~UTSR0_TFS);
} while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
}
static irqreturn_t sa1100_int(int irq, void *dev_id)
{
struct sa1100_port *sport = dev_id;
unsigned int status, pass_counter = 0;
spin_lock(&sport->port.lock);
status = UART_GET_UTSR0(sport);
status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
do {
if (status & (UTSR0_RFS | UTSR0_RID)) {
/* Clear the receiver idle bit, if set */
if (status & UTSR0_RID)
UART_PUT_UTSR0(sport, UTSR0_RID);
sa1100_rx_chars(sport);
}
/* Clear the relevant break bits */
if (status & (UTSR0_RBB | UTSR0_REB))
UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
if (status & UTSR0_RBB)
sport->port.icount.brk++;
if (status & UTSR0_REB)
uart_handle_break(&sport->port);
if (status & UTSR0_TFS)
sa1100_tx_chars(sport);
if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
break;
status = UART_GET_UTSR0(sport);
status &= SM_TO_UTSR0(sport->port.read_status_mask) |
~UTSR0_TFS;
} while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
spin_unlock(&sport->port.lock);
return IRQ_HANDLED;
}
