/** * @brief Low level HAL driver initialization. * * @notapi */ void hal_lld_init(void) { uint32_t reg; /* The system is switched to the RUN0 mode, the default for normal operations.*/ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } /* INTC initialization, software vector mode, 4 bytes vectors, starting at priority 0.*/ INTC.MCR.R = 0; INTC.CPR.R = 0; INTC.IACKR.R = (uint32_t)_vectors; /* PIT channel 0 initialization for Kernel ticks, the PIT is configured to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other modes.*/ INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY; halSPCSetPeripheralClockMode(92, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1; PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ PIT.CH[0].LDVAL.R = reg; PIT.CH[0].CVAL.R = reg; PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ /* EDMA initialization.*/ edmaInit(); }
/** * @brief Low level HAL driver initialization. * * @notapi */ void hal_lld_init(void) { uint32_t n; /* The system is switched to the RUN0 mode, the default for normal operations.*/ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } /* PIT_0 clock initialization.*/ halSPCSetPeripheralClockMode(30, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); /* TB counter enabled for debug and measurements.*/ asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */ "mtspr 1008, %%r3" /* HID0 register. */ : : : "r3"); /* PIT channel 0 initialization for Kernel ticks, the PIT is configured to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other modes.*/ INTC_PSR(226) = SPC5_PIT0_IRQ_PRIORITY; n = SPC5_AC12_DC4_CLK / OSAL_ST_FREQUENCY - 1; PIT_0.MCR.R = 1; /* Clock enabled, stop while debugging. */ PIT_0.CH[0].LDVAL.R = n; PIT_0.CH[0].CVAL.R = n; PIT_0.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT_0.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ /* EDMA initialization.*/ // edmaInit(); }
/** * @brief Low level HAL driver initialization. * * @notapi */ void hal_lld_init(void) { uint32_t n; /* The system is switched to the RUN0 mode, the default for normal operations.*/ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } #if SPC5_HSM_HANDSHAKE == 1 /* Notifies the HSM full clock initialization.*/ HT2HSMF = 2; #endif #if SPC5_HSM_HANDSHAKE == 2 /* Notifies the HSM full clock initialization by clearing WF_CC_DONE bit * Note that clearing a bit in HSM2HTF mailbox is done by writing 1 in the bit * * We also clear the CLK_CHG_RDY bit, no longer used */ HSM2HTF = WF_CC_DONE | CLK_CHG_RDY; #endif /* PIT_0 clock initialization.*/ halSPCSetPeripheralClockMode(30, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); /* TB counter enabled for debug and measurements.*/ asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */ "mtspr 1008, %%r3" /* HID0 register. */ : : : "r3"); /* PIT channel 0 initialization for Kernel ticks, the PIT is configured to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other modes.*/ INTC_PSR(226) = SPC5_PIT0_IRQ_PRIORITY; n = SPC5_AC12_DC4_CLK / OSAL_ST_FREQUENCY - 1; PIT_0.MCR.R = 1; /* Clock enabled, stop while debugging. */ PIT_0.TIMER[0].LDVAL.R = n; PIT_0.TIMER[0].CVAL.R = n; PIT_0.TIMER[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT_0.TIMER[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ /* EDMA initialization.*/ // edmaInit(); }
/** * @brief SPC5xx I/O ports configuration. * * @param[in] config the STM32 ports configuration * * @notapi */ void _pal_lld_init(const PALConfig *config) { unsigned i; #if defined(SPC5_SIUL_PCTL) /* SIUL clock gating if present.*/ halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); #endif /* Initialize PCR registers for undefined pads.*/ for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) { #if defined(SPC5_SIUL_SYSTEM_PINS) /* Handling the case where some SIU pins are not meant to be reprogrammed, for example JTAG pins.*/ unsigned j; for (j = 0; j < sizeof system_pins; j++) { if (i == system_pins[j]) goto skip; } SIU.PCR[i].R = config->default_mode; skip: ; #else SIU.PCR[i].R = config->default_mode; #endif } /* Initialize PADSEL registers.*/ for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++) SIU.PSMI[i].R = config->padsels[i]; /* Initialize PCR registers for defined pads.*/ i = 0; while (config->inits[i].pcr_index != -1) { SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value; SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value; i++; } }
/** * @brief SPC5xx I/O ports configuration. * * @param[in] config the SPC5xx ports configuration * * @notapi */ void _pal_lld_init(const PALConfig *config) { unsigned i; #if defined(SPC5_SIUL2_PCTL) /* SIUL clock gating if present.*/ halSPCSetPeripheralClockMode(SPC5_SIUL2_PCTL, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); #endif /* Initialize MSCR_MUX registers.*/ i = 0; while (config->mscr_mux[i].mscr_index != -1) { SIUL2.MSCR_MUX[config->mscr_mux[i].mscr_index].R = config->mscr_mux[i].mscr_value; i++; } /* Initialize MSCR_IO registers for defined pads.*/ i = 0; while (config->mscr_io[i].mscr_index != -1) { SIUL2.GPDO[config->mscr_io[i].mscr_index].R = config->mscr_io[i].gpdo_value; SIUL2.MSCR_IO[config->mscr_io[i].mscr_index].R = config->mscr_io[i].mscr_value; i++; } }
/** * @brief SPC560B/Cxx clocks and PLL initialization. * @note All the involved constants come from the file @p board.h and * @p hal_lld.h * @note This function must be invoked only after the system reset. * * @special */ void spc_clock_init(void) { /* Waiting for IRC stabilization before attempting anything else.*/ while (!ME.GS.B.S_FIRC) ; #if !SPC5_NO_INIT #if SPC5_DISABLE_WATCHDOG /* SWT disabled.*/ SWT.SR.R = 0xC520; SWT.SR.R = 0xD928; SWT.CR.R = 0xFF00000A; #endif /* SSCM initialization. Setting up the most restrictive handling of invalid accesses to peripherals.*/ SSCM.ERROR.R = 3; /* PAE and RAE bits. */ /* RGM errors clearing.*/ RGM.FES.R = 0xFFFF; RGM.DES.R = 0xFFFF; /* Oscillators dividers setup.*/ CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1; CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1; /* The system must be in DRUN mode on entry, if this is not the case then it is considered a serious anomaly.*/ if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) { SPC5_CLOCK_FAILURE_HOOK(); } #if defined(SPC5_OSC_BYPASS) /* If the board is equipped with an oscillator instead of a xtal then the bypass must be activated.*/ CGM.FXOSC_CTL.B.OSCBYP = TRUE; #endif /* SPC5_OSC_BYPASS */ /* Setting the various dividers and source selectors.*/ CGM.SC_DC0.R = SPC5_CGM_SC_DC0; CGM.SC_DC1.R = SPC5_CGM_SC_DC1; CGM.SC_DC2.R = SPC5_CGM_SC_DC2; /* Initialization of the FMPLLs settings.*/ CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF | ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) | (SPC5_FMPLL0_NDIV_VALUE << 16); CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */ /* Run modes initialization.*/ ME.IS.R = 8; /* Resetting I_ICONF status.*/ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */ ME.HALT.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */ ME.STOP.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */ ME.STANDBY.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */ if (ME.IS.B.I_ICONF) { /* Configuration rejected.*/ SPC5_CLOCK_FAILURE_HOOK(); } /* Peripherals run and low power modes initialization.*/ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS; ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS; ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS; ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS; ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS; ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS; ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS; ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS; ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS; ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS; ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS; ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS; ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS; ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS; ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS; ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS; /* CFLASH settings calculated for a maximum clock of 48MHz.*/ CFLASH.PFCR0.B.BK0_APC = 2; CFLASH.PFCR0.B.BK0_RWSC = 2; /* CMU clock enable */ halSPCSetPeripheralClockMode(104, SPC5_ME_PCTL_RUN(1) | SPC5_ME_PCTL_LP(2)); /* Switches again to DRUN mode (current mode) in order to update the settings.*/ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } #endif /* !SPC5_NO_INIT */ }