/**
* \brief SPI xDMA Rx callback
* Invoked on SPi DMA reception done.
* \param channel DMA channel.
* \param pArg Pointer to callback argument - Pointer to Spid instance.
*/
static void SPID_Rx_Cb(uint32_t channel, Spid* pArg)
{
SpidCmd *pSpidCmd = pArg->pCurrentCommand;
Spi *pSpiHw = pArg->pSpiHw;
if (channel != spiDmaRxChannel)
return;
/* Disable the SPI TX & RX */
SPI_Disable ( pSpiHw );
/* Configure and enable interrupt on RC compare */
NVIC_ClearPendingIRQ(XDMAC_IRQn);
NVIC_DisableIRQ(XDMAC_IRQn);
/* Disable the SPI Peripheral */
PMC_DisablePeripheral ( pArg->spiId );
/* Release CS */
SPI_ReleaseCS(pSpiHw);
/* Release the DMA channels */
XDMAD_FreeChannel(pArg->pXdmad, spiDmaRxChannel);
XDMAD_FreeChannel(pArg->pXdmad, spiDmaTxChannel);
/* Release the dataflash semaphore */
pArg->semaphore++;
printf("\n\r%s\n\r",pArg->pCurrentCommand->pRxBuff);
/* Invoke the callback associated with the current command */
if (pSpidCmd && pSpidCmd->callback) {
//printf("p %d", pArg->semaphore);
pSpidCmd->callback(0, pSpidCmd->pArgument);
}
}
static BOOL SPI_Config(LPC_SSP_T *spi, int Bits, int Mode, int Slave)
{
SPI_Disable(spi);
if (!(Bits >= 4 && Bits <= 16) || !(Mode >= 0 && Mode <= 3)) {
return FALSE; // SPI format error
}
int polarity = (Mode & 0x2) ? 1 : 0;
int phase = (Mode & 0x1) ? 1 : 0;
// set it up
int DSS = Bits - 1; // DSS (data select size)
int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
int SPH = (phase) ? 1 : 0; // SPH - clock out phase
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = spi->CR0;
tmp &= ~(0xFFFF);
tmp |= DSS << 0
| FRF << 4
| SPO << 6
| SPH << 7;
spi->CR0 = tmp;
tmp = spi->CR1;
tmp &= ~(0xD);
tmp |= 0 << 0 // LBM - loop back mode - off
| ((Slave) ? 1 : 0) << 2 // MS - master Slave mode, 1 = Slave
| 0 << 3; // SOD - slave output disable - na
spi->CR1 = tmp;
SPI_Enable(spi);
return TRUE;
}
static BOOL SPI_Frequency(LPC_SSP_T *spi, int Hz)
{
SPI_Disable(spi);
uint32_t PCLK = SystemCoreClock;
int prescaler;
for (prescaler = 2; prescaler <= 254; prescaler += 2) {
int prescale_Hz = PCLK / prescaler;
// calculate the divider
int divider = floor(((float)prescale_Hz / (float)Hz) + 0.5f);
// check we can support the divider
if (divider < 256) {
// prescaler
spi->CPSR = prescaler;
// divider
spi->CR0 &= ~(0xFFFF << 8);
spi->CR0 |= (divider - 1) << 8;
SPI_Enable(spi);
return TRUE;
}
}
return FALSE; // Couldn't setup requested SPI frequency
}
byte MMC_Release(byte result)
{
MMC_SS_HIGH();
SPI_ReceiveByte(0xFF); // CS does not release SPI until next clock....flush CS release
SPI_Disable();
return result;
}
void Hardware_::GetAccelerometer(signed char* xyz)
{
SPI_Enable();
SPCR = 0x50;
AACCS_SS_LOW();
for (u8 i = 0; i < 3; i++)
xyz[i] = ReadAcc(i+6);
AACCS_SS_HIGH();
SPI_Disable();
}
void Accelerometer_Init()
{
SPI_Enable();
SPCR = 0x50;
AACCS_SS_LOW();
WriteAcc(0x0D,0x80); // Disable I2C
WriteAcc(0x16,0x05); // Init 2G
AACCS_SS_HIGH();
SPI_Disable();
}
/** Shuts down the current selected SPI driver (hardware or software, depending on the selected ISP speed) so that no
* further communications can occur until the driver is re-initialized.
*/
void ISPTarget_DisableTargetISP(void)
{
if (HardwareSPIMode)
{
SPI_Disable();
}
else
{
DDRB &= ~((1 << 1) | (1 << 2));
PORTB &= ~((1 << 0) | (1 << 3));
/* Must re-enable rescue clock once software ISP has exited, as the timer for the rescue clock is
* re-purposed for software SPI */
ISPTarget_ConfigureRescueClock();
}
}
BOOL CPU_SPI_Xaction_Stop(const SPI_CONFIGURATION& Configuration)
{
LPC_SSP_T *spi = SPI_REG(Configuration.SPI_mod);
while (SPI_Busy(spi)); // wait for completion
if(Configuration.CS_Hold_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled(Configuration.CS_Hold_uSecs);
}
CPU_GPIO_SetPinState(Configuration.DeviceCS, !Configuration.CS_Active);
GPIO_RESISTOR res = RESISTOR_PULLDOWN;
if (Configuration.MSK_IDLE) res = RESISTOR_PULLUP;
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
CPU_GPIO_EnableInputPin(msk, FALSE, NULL, GPIO_INT_NONE, res);
CPU_GPIO_EnableInputPin(miso, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLDOWN);
CPU_GPIO_EnableInputPin(mosi, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLDOWN);
SPI_Disable(spi); // Disable SPI
return TRUE;
}
void SPI_SetConfig(SpiConfigData_t* config)
{
uint8_t spiMode;
csPin = config->CsPin;
csPolarity = config->CsPolarity;
switch(config->SpiMode)
{
case 0:
spiMode = SPI0_CLKMODE_0;
break;
case 1:
spiMode = SPI0_CLKMODE_1;
break;
case 2:
spiMode = SPI0_CLKMODE_2;
break;
case 3:
spiMode = SPI0_CLKMODE_3;
break;
}
if(config->IsEnabled)
{
SFRPAGE = 0x20;
SPI0CKR = config->CkrVal;
SPI0_init(spiMode, true, false);
SPI_Enable();
if(csPin != 0)
{
GPIO_MakeOutput(csPin, PushPullOutput);
GPIO_WriteValue(csPin, !csPolarity);
}
}
else
SPI_Disable();
}
void SPIClass::end() {
SPI_Disable(spi);
}
void SPIClass::end() {
SPI_Disable(spi);
initialized = false;
}
static rt_err_t configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
struct tina_spi_cs *tina_spi_cs = device->parent.user_data;
struct tina_spi *_spi_info = (struct tina_spi *)spi_bus->parent.user_data;
SPI_T *spi = _spi_info->spi;
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
DEBUG_PRINTF("spi address: %08X\n", (rt_uint32_t)spi);
SPI_Disable(spi);
SPI_Reset(spi);
SPI_ResetRxFifo(spi);
SPI_ResetTxFifo(spi);
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
/* data_width */
if (configuration->data_width != 8)
{
DEBUG_PRINTF("error: data_width is %d\n", configuration->data_width);
return RT_EIO;
}
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
SPI_SetDuplex(spi, SPI_TCTRL_DHB_FULL_DUPLEX);
SPI_SetMode(spi, SPI_CTRL_MODE_MASTER);
/* MSB or LSB */
if (configuration->mode & RT_SPI_MSB)
{
SPI_SetFirstTransmitBit(spi, SPI_TCTRL_FBS_MSB);
}
else
{
SPI_SetFirstTransmitBit(spi, SPI_TCTRL_FBS_LSB);
}
switch (configuration->mode)
{
case RT_SPI_MODE_0:
SPI_SetSclkMode(spi, SPI_SCLK_Mode0);
break;
case RT_SPI_MODE_1:
SPI_SetSclkMode(spi, SPI_SCLK_Mode1);
break;
case RT_SPI_MODE_2:
SPI_SetSclkMode(spi, SPI_SCLK_Mode2);
break;
case RT_SPI_MODE_3:
SPI_SetSclkMode(spi, SPI_SCLK_Mode3);
break;
}
/* baudrate */
{
unsigned int spi_clock = 0;
rt_uint32_t max_hz;
rt_uint32_t div;
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
max_hz = configuration->max_hz;
if (max_hz > SPI_BUS_MAX_CLK)
{
max_hz = SPI_BUS_MAX_CLK;
}
spi_clock = ahb_get_clk();
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
div = (spi_clock + max_hz - 1) / max_hz;
dbg_log(DBG_LOG, "configuration->max_hz: %d\n", configuration->max_hz);
dbg_log(DBG_LOG, "max freq: %d\n", max_hz);
dbg_log(DBG_LOG, "spi_clock: %d\n", spi_clock);
dbg_log(DBG_LOG, "div: %d\n", div);
SPI_SetClkDiv(spi, div / 2);
} /* baudrate */
SPI_ManualChipSelect(spi, tina_spi_cs->cs);
SPI_SetDataSize(spi, 0, 0);
SPI_Enable(spi);
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
return RT_EOK;
};
/**
* \brief Reset the ADS7843
*/
void ADS7843_Reset( void )
{
/* Disable SPI */
SPI_Disable( BOARD_TSC_SPI_BASE ) ;
}
//------------------------------------------------------------------------------
uint8_t serialProcess(void)
{
uint8_t cmd = RingBuffer_Remove(&buffer_);
uint8_t size = RingBuffer_Remove(&buffer_);
if(cmd == SERIAL_START_CONFIG)
{
return xilinxSetupConfiguration();
}
else if(cmd == SERIAL_DOWNLOAD_DATA)
{
uint8_t i=0;
LEDs_ToggleLEDs(LEDS_LED1);
for(i=0; i<size; i++)
{
xilinxSend(RingBuffer_Remove(&buffer_));
}
if(isSetDone())
{
return true;
}
if(!isSetInitB())
{
return false;
}
}
else if(cmd == SERIAL_USE_SPI)
{
SPI_Init(SPI_SPEED_FCPU_DIV_8 |
SPI_SCK_LEAD_RISING |
SPI_SAMPLE_LEADING |
SPI_ORDER_MSB_FIRST |
SPI_MODE_MASTER);
DDRB |= (1 << 0);
PORTB |= (1 << 0);
}
else if(cmd == SERIAL_SPI_DATA)
{
uint8_t i=0;
LEDs_ToggleLEDs(LEDS_LED2);
for(i=0; i<size; i++)
{
SPI_SendByte(RingBuffer_Remove(&buffer_));
}
}
else if(cmd == SERIAL_SPI_SELECT)
{
uint8_t prop = RingBuffer_Remove(&buffer_);
if(prop)
{
PORTD &= ~_BV(PD3);
}
else
{
PORTD |= _BV(PD3);
}
}
else if(cmd == SERIAL_USE_USART)
{
SPI_Disable();
PORTB &= ~((1 << 1) | (1 << 2));
DDRB |= (1 << 1) | (1 << 2);
}
else if(cmd == SERIAL_USART_DATA)
{
uint8_t i=0;
for(i=0; i<size; i++)
{
Serial_SendByte(RingBuffer_Remove(&buffer_));
}
}
else if(cmd == SERIAL_FPGA_RESET)
{
PORTB |= _BV(PB1);
_delay_us(5);
PORTB &= ~_BV(PB1);
}
else if(cmd == SERIAL_FPGA_START)
{
PORTB |= _BV(PB2);
_delay_us(5);
PORTB &= ~_BV(PB2);
}
else
{
uint8_t i=0;
for(i=0; i<size; i++)
RingBuffer_Remove(&buffer_);
return false;
}
return true;
}
