Пример #1
0
static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
        struct spi_imx_config *config)
{
    u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;

    /* set master mode */
    ctrl |= SPI_IMX2_3_CTRL_MODE(config->cs);

    /* set clock speed */
    ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);

    /* set chip select to use */
    ctrl |= SPI_IMX2_3_CTRL_CS(config->cs);

    ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET;

    cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs);

    if (config->mode & SPI_CPHA)
        cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs);

    if (config->mode & SPI_CPOL)
        cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs);

    if (config->mode & SPI_CS_HIGH)
        cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs);

    writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL);
    writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG);

    return 0;
}
Пример #2
0
static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
		struct spi_imx_config *config)
{
	u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;

	/*
	 * The hardware seems to have a race condition when changing modes. The
	 * current assumption is that the selection of the channel arrives
	 * earlier in the hardware than the mode bits when they are written at
	 * the same time.
	 * So set master mode for all channels as we do not support slave mode.
	 */
	ctrl |= SPI_IMX2_3_CTRL_MODE_MASK;

	/* set clock speed */
	ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);

	/* set chip select to use */
	ctrl |= SPI_IMX2_3_CTRL_CS(config->cs);

	ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET;

	cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs);

	if (config->mode & SPI_CPHA)
		cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs);

	if (config->mode & SPI_CPOL)
		cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs);

	if (config->mode & SPI_CS_HIGH)
		cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs);

	writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL);
	writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG);

	return 0;
}