/**
* @brief Erase whole SPI flash memory.
* @param spi is the base address of SPI module.
* @return None.
* @note Before calling this function, the transaction length (data width) must be configured as 8 bits.
*/
void SpiFlash_ChipErase(SPI_T *spi)
{
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x06: Write enable */
SPI_WRITE_TX0(spi, 0x06);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
__NOP();
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0xC7: Chip erase */
SPI_WRITE_TX0(spi, 0xC7);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
}
void SpiFlash_WriteStatusReg(uint8_t u8Value)
{
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x06, Write enable
SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
///////////////////////////////////////
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x01, Write status register
SPI_WRITE_TX(SPI_FLASH_PORT, 0x01);
// write status
SPI_WRITE_TX(SPI_FLASH_PORT, u8Value);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
}
void SpiFlash_ChipErase(void)
{
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x06, Write enable
SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
//////////////////////////////////////////
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0xC7, Chip Erase
SPI_WRITE_TX(SPI_FLASH_PORT, 0xC7);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
SPI_ClearRxFIFO(SPI0);
}
/**
* @brief Read SPI flash memory.
* @param spi is the base address of SPI module.
* @param u32StartAddress is the start address.
* @param au8DataBuffer is the pointer of destination buffer.
* @param u32ByteCount is the total data count.
* @return None.
* @note Before calling this function, the transaction length (data width) must be configured as 8 bits.
*/
void SpiFlash_ReadData(SPI_T *spi, uint32_t u32StartAddress, uint8_t *au8DataBuffer, uint32_t u32ByteCount)
{
uint32_t u32RxCounter;
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x03: Read data */
SPI_WRITE_TX0(spi, 0x03);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send 24-bit start address */
/* Send the first 8 address bits */
SPI_WRITE_TX0(spi, (u32StartAddress >> 16) & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send the second 8 address bits */
SPI_WRITE_TX0(spi, (u32StartAddress >> 8) & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send the third 8 address bits */
SPI_WRITE_TX0(spi, u32StartAddress & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Reset RX data counter */
u32RxCounter = 0;
while(u32RxCounter < u32ByteCount)
{
/* Send SPI bus clock to get data from SPI flash */
SPI_WRITE_TX0(spi, 0x00);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Read data */
au8DataBuffer[u32RxCounter++] = SPI_READ_RX0(spi);
}
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
}
uint16_t SpiFlash_ReadMidDid(void)
{
uint8_t u8RxData[6], u8IDCnt = 0;
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x90, Read Manufacturer/Device ID
SPI_WRITE_TX(SPI_FLASH_PORT, 0x90);
// send 24-bit '0', dummy
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// receive 16-bit
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
while(!SPI_GET_RX_FIFO_EMPTY_FLAG(SPI_FLASH_PORT))
u8RxData[u8IDCnt ++] = SPI_READ_RX(SPI_FLASH_PORT);
return ( (u8RxData[4]<<8) | u8RxData[5] );
}
void LCD_WriteData(uint8_t u8Data)
{
ILI9341_DC = 1;
SPI_WRITE_TX(SPI_LCD_PORT, u8Data);
// wait tx finish
while(SPI_IS_BUSY(SPI_LCD_PORT));
}
void LCD_WriteCommand(uint8_t u8Comm)
{
ILI9341_DC = 0;
SPI_WRITE_TX(SPI_LCD_PORT, u8Comm);
// wait tx finish
while(SPI_IS_BUSY(SPI_LCD_PORT));
}
void SpiFlash_NormalPageProgram(uint32_t StartAddress, uint8_t *u8DataBuffer)
{
uint32_t i = 0;
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x06, Write enable
SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x02, Page program
SPI_WRITE_TX(SPI_FLASH_PORT, 0x02);
// send 24-bit start address
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress & 0xFF);
// write data
while(1) {
if(!SPI_GET_TX_FIFO_FULL_FLAG(SPI_FLASH_PORT)) {
SPI_WRITE_TX(SPI_FLASH_PORT, u8DataBuffer[i++]);
if(i >= 255) break;
}
}
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
SPI_ClearRxFIFO(SPI_FLASH_PORT);
}
void SpiFlash_DualFastRead(uint32_t StartAddress, uint8_t *u8DataBuffer)
{
uint32_t i;
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// Command: 0x3B, Fast Read dual data
SPI_WRITE_TX(SPI_FLASH_PORT, 0x3B);
// send 24-bit start address
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8) & 0xFF);
SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress & 0xFF);
// dummy byte
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// clear RX buffer
SPI_ClearRxFIFO(SPI_FLASH_PORT);
// enable SPI dual IO mode and set direction to input
SPI_ENABLE_DUAL_MODE(SPI_FLASH_PORT);
SPI_ENABLE_DUAL_INPUT_MODE(SPI_FLASH_PORT);
// read data
for(i=0; i<256; i++) {
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
while(SPI_IS_BUSY(SPI_FLASH_PORT));
u8DataBuffer[i] = SPI_READ_RX(SPI_FLASH_PORT);
}
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
SPI_DISABLE_DUAL_MODE(SPI_FLASH_PORT);
}
/* ----------------------------------------------------------------------------
* Function : void EEPROM_Write_Init(uint32_t spi_interface,
* uint16_t address)
* ----------------------------------------------------------------------------
* Description : Ready the EEPROM for writing at a specified address. Chip
* select is left low.
* Inputs : - spi_interface - Index of SPI interface; use 0, 1
* - address - EEPROM address to write to
* Outputs : None
* Assumptions : EEPROM is write enabled
* ------------------------------------------------------------------------- */
void EEPROM_Write_Init(uint32_t spi_interface, uint16_t address)
{
/* Check if SPI interface exists. If interface is invalid, return. */
if(spi_interface > (EEPROM_SPI_NUM_INTERFACE - 1))
{
return;
}
/* Send write opcode */
SPI_WRITE(spi_interface, EEPROM_OPCODE_WRITE);
SPI_TRANSFERCONFIG(spi_interface, EEPROM_SPI_WRITE_BYTE);
while(SPI_IS_BUSY(spi_interface));
/* Send address to write to */
SPI_WRITE(spi_interface, address);
SPI_TRANSFERCONFIG(spi_interface, EEPROM_SPI_WRITE_SHORT);
while(SPI_IS_BUSY(spi_interface));
/* NOTE: Chip select is left low. */
}
uint8_t TM_SPI_DMA_Transmitting(SPI_TypeDef* SPIx) {
/* Get SPI settings */
TM_SPI_DMA_INT_t* Settings = TM_SPI_DMA_INT_GetSettings(SPIx);
/* Check if TX or RX DMA are working */
return (
Settings->RX_Stream->NDTR || /*!< RX is working */
Settings->TX_Stream->NDTR || /*!< TX is working */
SPI_IS_BUSY(SPIx) /*!< SPI is busy */
);
}
void Display_SSD_Write(uint8_t isData, const uint8_t *buf, uint32_t len) {
int i;
// Set D/C#
DISPLAY_SSD_DC = isData ? 1 : 0;
for(i = 0; i < len; i++) {
// Send byte, wait until it is transmitted
SPI_WRITE_TX(SPI0, buf[i]);
while(SPI_IS_BUSY(SPI0));
}
}
/**
* @brief Write SPI flash status register.
* @param spi is the base address of SPI module.
* @param u32Value is the value attempt to write to status register.
* @return None.
* @note Before calling this function, the transaction length (data width) must be configured as 8 bits.
*/
void SpiFlash_WriteStatusReg(SPI_T *spi, uint32_t u32Value)
{
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x06: Write enable */
SPI_WRITE_TX0(spi, 0x06);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
__NOP();
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x01: Write status register */
SPI_WRITE_TX0(spi, 0x01);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* write to status register 1 */
SPI_WRITE_TX0(spi, u32Value & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* write to status register 2 */
SPI_WRITE_TX0(spi, (u32Value >> 8) & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
}
/* ----------------------------------------------------------------------------
* Function : void EEPROM_Write_Byte(uint32_t spi_interface,
* uint8_t data)
* ----------------------------------------------------------------------------
* Description : Write a byte to the EEPROM
* Inputs : - spi_interface - Index of SPI interface; use 0, 1
* - data - Byte to write
* Outputs : None
* Assumptions : - EEPROM is initialized to an address
* - Current EEPROM address is outside write protected blocks
* - EEPROM is selected by chip select
* ------------------------------------------------------------------------- */
void EEPROM_Write_Byte(uint32_t spi_interface, uint8_t data)
{
/* Check if SPI interface exists. If interface is invalid, return. */
if (spi_interface > (EEPROM_SPI_NUM_INTERFACE - 1))
{
return;
}
SPI_WRITE(spi_interface, data);
SPI_TRANSFERCONFIG(spi_interface, EEPROM_SPI_WRITE_BYTE);
while (SPI_IS_BUSY(spi_interface));
/* NOTE: Chip select is left low. */
}
/**
* @brief Read SPI flash manufacturer ID and device ID.
* @param spi is the base address of SPI module.
* @return High byte is manufacturer ID; low byte is device ID.
* @note Before calling this function, the transaction length (data width) must be configured as 8 bits.
*/
uint32_t SpiFlash_ReadMidDid(SPI_T *spi)
{
uint32_t u32MID_DID;
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x90: Read Manufacturer/Device ID */
SPI_WRITE_TX0(spi, 0x90);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send total 24 '0' dummy bits */
/* Send the first 8 dummy bits */
SPI_WRITE_TX0(spi, 0x00);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send the second 8 dummy bits */
SPI_WRITE_TX0(spi, 0x00);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send the third 8 dummy bits */
SPI_WRITE_TX0(spi, 0x00);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send SPI bus clock to get the Manufacturer ID */
SPI_WRITE_TX0(spi, 0x00);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Get the Manufacturer ID */
u32MID_DID = spi->RX0 << 8;
/* Send SPI bus clock to get the Device ID */
SPI_WRITE_TX0(spi, 0x00);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Get the Device ID */
u32MID_DID |= spi->RX0;
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
return u32MID_DID;
}
/* ----------------------------------------------------------------------------
* Function : uint8_t EEPROM_Read_Byte(uint32_t spi_interface)
* ----------------------------------------------------------------------------
* Description : Read a byte from the EEPROM
* Inputs : spi_interface - Index of SPI interface; use 0, 1
* Outputs : data - Byte read (return 0xFF if the specified
* SPI interface is invalid)
* Assumptions : - EEPROM is initialized to an address
* - EEPROM is selected by chip select
* ------------------------------------------------------------------------- */
uint8_t EEPROM_Read_Byte(uint32_t spi_interface)
{
/* Check if SPI interface exists. If interface is invalid, return 0xFF. */
if(spi_interface > (EEPROM_SPI_NUM_INTERFACE - 1))
{
return 0xFF;
}
SPI_TRANSFERCONFIG(spi_interface, EEPROM_SPI_READ_BYTE);
while(SPI_IS_BUSY(spi_interface));
return (uint8_t)SPI_READ(spi_interface);
/* NOTE: Chip select is left low. */
}
/**
* @brief Read SPI flash status register.
* @param spi is the base address of SPI module.
* @return Status register value.
* @note Before calling this function, the transaction length (data width) must be configured as 8 bits.
*/
uint32_t SpiFlash_ReadStatusReg(SPI_T *spi)
{
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x05: Read status register */
SPI_WRITE_TX0(spi, 0x05);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send SPI bus clock to read status register */
SPI_WRITE_TX0(spi, 0x00);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
/* Return the status register value */
return (spi->RX0);
}
int spi_write_packet(SPI_T *spi, uint8_t *data, int len)
{
int timeout, i;
for(i=0; len != 0; i++, len--) {
SPI_WRITE_TX0(spi, data[i]);
SPI_TRIGGER(spi);
timeout = SPI_TIMEOUT;
while(SPI_IS_BUSY(spi)) {
if(!timeout--) {
return(-1);
}
}
}
return(0);
}
uint8_t LCD_ReadReg(uint8_t u8Comm)
{
SPI_ClearRxFIFO(SPI_LCD_PORT);
ILI9341_DC = 0;
SPI_WRITE_TX(SPI_LCD_PORT, u8Comm);
SPI_WRITE_TX(SPI_LCD_PORT, 0x00);
// wait tx finish
while(SPI_IS_BUSY(SPI_LCD_PORT));
SPI_READ_RX(SPI_LCD_PORT);
return (SPI_READ_RX(SPI_LCD_PORT));
}
int spi_read_packet(SPI_T *spi, uint8_t *data, int len)
{
int timeout, i;
for(i=0; len != 0; i++, len--) {
timeout = SPI_TIMEOUT;
SPI_WRITE_TX0(spi, 0);
SPI_TRIGGER(spi);
while(SPI_IS_BUSY(spi)) {
if(!timeout--) {
printf("spi_read_packet timeout (len = %d)\n",len);
return(-1);
}
}
data[i] = SPI_READ_RX0(spi);
}
return(0);
}
uint8_t SpiFlash_ReadStatusReg(void)
{
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x05, Read status register
SPI_WRITE_TX(SPI_FLASH_PORT, 0x05);
// read status
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
// skip first rx data
SPI_READ_RX(SPI_FLASH_PORT);
return (SPI_READ_RX(SPI_FLASH_PORT) & 0xff);
}
/**
* @brief Perform SPI flash page program.
* @param spi is the base address of SPI module.
* @param u32StartAddress is the start address.
* @param au8DataBuffer is the pointer of source data.
* @param u32ByteCount is the total data count. The maximum number is 256.
* @return None.
* @note Before calling this function, the transaction length (data width) must be configured as 8 bits.
*/
void SpiFlash_PageProgram(SPI_T *spi, uint32_t u32StartAddress, uint8_t *au8DataBuffer, uint32_t u32ByteCount)
{
uint32_t u32Counter;
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x06: Write enable */
SPI_WRITE_TX0(spi, 0x06);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
__NOP();
/* /CS: active */
SPI_SET_SS_LOW(spi);
/* Send command 0x02: Page program */
SPI_WRITE_TX0(spi, 0x02);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send 24-bit start address */
/* Send the first 8 address bits */
SPI_WRITE_TX0(spi, (u32StartAddress >> 16) & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send the second 8 address bits */
SPI_WRITE_TX0(spi, (u32StartAddress >> 8) & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Send the third 8 address bits */
SPI_WRITE_TX0(spi, u32StartAddress & 0xFF);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
/* Check busy state */
while(SPI_IS_BUSY(spi));
u32Counter = 0;
while(u32Counter < u32ByteCount)
{
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* Write one byte to SPI flash */
SPI_WRITE_TX0(spi, au8DataBuffer[u32Counter++]);
/* Trigger SPI transfer */
SPI_TRIGGER(spi);
}
/* Check busy state */
while(SPI_IS_BUSY(spi));
/* /CS: inactive */
SPI_SET_SS_HIGH(spi);
}
/* Envía un valor de 16 bits, count veces */
uint16_t SPI_DMA_SendHalfWord(SPI_TypeDef* SPIx, uint16_t value, uint16_t count){
uint16_t dummy = value;
uint32_t tmp;
/* 16 bits */
SPI_DataSizeConfig(SPIx, SPI_DataSize_16b);
/* Establece el tamaño de 16 bits al bus de datos a transmitir */
SPI_DMA_InitStruct.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
SPI_DMA_InitStruct.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
/* Configura la dirección del Periférico y la cantidad de bytes a escribir */
SPI_DMA_InitStruct.DMA_PeripheralBaseAddr = (uint32_t)(&(SPIx->DR));
SPI_DMA_InitStruct.DMA_BufferSize = count;
/*********************** TRANSMIT ****************************/
/* Configura el TX DMA */
SPI_DMA_InitStruct.DMA_DIR = SPI_DMA_DIR_TX; /* Memory to Peripheral */
SPI_DMA_InitStruct.DMA_MemoryBaseAddr = (uint32_t)&dummy;
SPI_DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Clear TX DMA1 FLAG y comienza la transmisión */
if(SPIx == SPI1){
DMA_ClearFlag(SPI1_TX_DMA_CHANNEL_FLAG); /* SPI1 */
DMA_Init(SPI1_TX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
else if(SPIx == SPI2){
DMA_ClearFlag(SPI2_TX_DMA_CHANNEL_FLAG); /* SPI2 */
DMA_Init(SPI2_TX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#if defined(L152RE)
else{
DMA_ClearFlag(SPI3_TX_DMA_CHANNEL_FLAG); /* SPI3 */
DMA_Init(SPI3_TX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#endif
/*************** RECEIVE TO CLEAR BUFFER *****************/
/* Configura el RX DMA */
SPI_DMA_InitStruct.DMA_DIR = SPI_DMA_DIR_RX; /* Peripheral to Memory */
SPI_DMA_InitStruct.DMA_MemoryBaseAddr = (uint32_t)&tmp;
SPI_DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Clear RX DMA1 FLAG y comienza la transmisión */
if(SPIx == SPI1){
DMA_ClearFlag(SPI1_RX_DMA_CHANNEL_FLAG); /* SPI1 */
DMA_Init(SPI1_RX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
else if(SPIx == SPI2){
DMA_ClearFlag(SPI2_RX_DMA_CHANNEL_FLAG); /* SPI2 */
DMA_Init(SPI2_RX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#if defined(L152RE)
else{
DMA_ClearFlag(SPI3_RX_DMA_CHANNEL_FLAG); /* SPI3 */
DMA_Init(SPI3_RX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#endif
/************************ HABILITACIÓN **************************/
if(SPIx == SPI1){
DMA_Cmd(SPI1_TX_DMA_CHANNEL,ENABLE);
DMA_Cmd(SPI1_RX_DMA_CHANNEL,ENABLE);
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
while ((DMA_GetFlagStatus(SPI1_RX_DMA_CHANNEL_FLAG) == RESET) | SPI_IS_BUSY(SPI1));
DMA_Cmd(SPI1_TX_DMA_CHANNEL,DISABLE);
DMA_Cmd(SPI1_RX_DMA_CHANNEL,DISABLE);
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
}
else if(SPIx == SPI2){
DMA_Cmd(SPI2_TX_DMA_CHANNEL,ENABLE);
DMA_Cmd(SPI2_RX_DMA_CHANNEL,ENABLE);
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
while ((DMA_GetFlagStatus(SPI2_RX_DMA_CHANNEL_FLAG) == RESET) | SPI_IS_BUSY(SPI2));
DMA_Cmd(SPI2_TX_DMA_CHANNEL,DISABLE);
DMA_Cmd(SPI2_RX_DMA_CHANNEL,DISABLE);
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
}
#if defined(L152RE)
else{
DMA_Cmd(SPI3_TX_DMA_CHANNEL,ENABLE);
DMA_Cmd(SPI3_RX_DMA_CHANNEL,ENABLE);
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
while ((DMA_GetFlagStatus(SPI3_RX_DMA_CHANNEL_FLAG) == RESET) | SPI_IS_BUSY(SPI3));
DMA_Cmd(SPI3_TX_DMA_CHANNEL,DISABLE);
DMA_Cmd(SPI3_RX_DMA_CHANNEL,DISABLE);
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
}
#endif
return (uint16_t)tmp;
}
/* Envía y recibe datos de 8 bits (SPI-DMA) */
uint8_t SPI_DMA_Transmit8(SPI_TypeDef* SPIx, const uint8_t* pTData, uint8_t* pRData, uint16_t pSize){
uint32_t Dummy = 0xFF;
/* Establece el tamaño de 8 bits al bus de datos a transmitir */
SPI_DMA_InitStruct.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
SPI_DMA_InitStruct.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
/* Configura la dirección del Periférico y la cantidad de bytes a escribir */
SPI_DMA_InitStruct.DMA_PeripheralBaseAddr = (uint32_t)(&(SPIx->DR));
SPI_DMA_InitStruct.DMA_BufferSize = pSize;
/* 8 bits */
SPI_DataSizeConfig(SPIx, SPI_DataSize_8b);
/*********************** TRANSMIT ****************************/
/* Configura el TX DMA */
SPI_DMA_InitStruct.DMA_DIR = SPI_DMA_DIR_TX; /* Memory to Peripheral */
if(pTData){
SPI_DMA_InitStruct.DMA_MemoryBaseAddr = (uint32_t)pTData;
SPI_DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Enable;
}else{
SPI_DMA_InitStruct.DMA_MemoryBaseAddr = (uint32_t)&Dummy;
SPI_DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Disable;
}
/* Clear TX DMA1 FLAG y comienza la transmisión */
if(SPIx == SPI1){
DMA_ClearFlag(SPI1_TX_DMA_CHANNEL_FLAG); /* SPI1 */
DMA_Init(SPI1_TX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
else if(SPIx == SPI2){
DMA_ClearFlag(SPI2_TX_DMA_CHANNEL_FLAG); /* SPI2 */
DMA_Init(SPI2_TX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#if defined(L152RE)
else{
DMA_ClearFlag(SPI3_TX_DMA_CHANNEL_FLAG); /* SPI3 */
DMA_Init(SPI3_TX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#endif
/************************** RECEIVE ****************************/
/* Configura el RX DMA */
SPI_DMA_InitStruct.DMA_DIR = SPI_DMA_DIR_RX; /* Peripheral to Memory */
if(pRData){
SPI_DMA_InitStruct.DMA_MemoryBaseAddr = (uint32_t)pRData;
SPI_DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Enable;
}else{
SPI_DMA_InitStruct.DMA_MemoryBaseAddr = (uint32_t)&Dummy;
SPI_DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Disable;
}
/* Clear RX DMA1 FLAG y comienza la transmisión */
if(SPIx == SPI1){
DMA_ClearFlag(SPI1_RX_DMA_CHANNEL_FLAG); /* SPI1 */
DMA_Init(SPI1_RX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
else if(SPIx == SPI2){
DMA_ClearFlag(SPI2_RX_DMA_CHANNEL_FLAG); /* SPI2 */
DMA_Init(SPI2_RX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#if defined(L152RE)
else{
DMA_ClearFlag(SPI3_RX_DMA_CHANNEL_FLAG); /* SPI3 */
DMA_Init(SPI3_RX_DMA_CHANNEL,&SPI_DMA_InitStruct);
}
#endif
/************************ HABILITACIÓN **************************/
if(SPIx == SPI1){
DMA_Cmd(SPI1_TX_DMA_CHANNEL,ENABLE);
DMA_Cmd(SPI1_RX_DMA_CHANNEL,ENABLE);
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
while ((DMA_GetFlagStatus(SPI1_RX_DMA_CHANNEL_FLAG) == RESET) | SPI_IS_BUSY(SPI1));
DMA_Cmd(SPI1_TX_DMA_CHANNEL,DISABLE);
DMA_Cmd(SPI1_RX_DMA_CHANNEL,DISABLE);
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
}
else if(SPIx == SPI2){
DMA_Cmd(SPI2_TX_DMA_CHANNEL,ENABLE);
DMA_Cmd(SPI2_RX_DMA_CHANNEL,ENABLE);
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
while ((DMA_GetFlagStatus(SPI2_RX_DMA_CHANNEL_FLAG) == RESET) | SPI_IS_BUSY(SPI2));
DMA_Cmd(SPI2_TX_DMA_CHANNEL,DISABLE);
DMA_Cmd(SPI2_RX_DMA_CHANNEL,DISABLE);
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
}
#if defined(L152RE)
else{
DMA_Cmd(SPI3_TX_DMA_CHANNEL,ENABLE);
DMA_Cmd(SPI3_RX_DMA_CHANNEL,ENABLE);
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
while ((DMA_GetFlagStatus(SPI3_RX_DMA_CHANNEL_FLAG) == RESET) | SPI_IS_BUSY(SPI3));
DMA_Cmd(SPI3_TX_DMA_CHANNEL,DISABLE);
DMA_Cmd(SPI3_RX_DMA_CHANNEL,DISABLE);
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
}
#endif
return 1;
}
