uint8_t Check_ACK_master(uint8_t clear)
{
// while(ioport_get_value(nrf24l01M_IRQ));//IRQ is active low, so if there is no event, in the loop
//sta = SPI_MasterTransceiveByte(&spiMasterC, 0xff);
sta = rf_readreg_master(STATUSREG);
/*
do{
}while(!USART_IsTXDataRegisterEmpty(&USART));
USART_PutChar(&USART, sta);
*/
SPI_MasterTransceiveByte(&spiMasterF, FLUSH_TX);
rf_writereg_master(WRITE_REG + STATUSREG, sta);
SPI_MasterTransceiveByte(&spiMasterF, FLUSH_TX);
/* //IRQ = 1;
ioport_configure_pin(nrf24l01M_IRQ, IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH);
ioport_set_pin_high(nrf24l01M_IRQ);
ioport_configure_pin(nrf24l01M_IRQ, IOPORT_DIR_INPUT);
*/
if (TX_DS)
return 0x00;
else
return 0xff;
}
uint8_t rf_writereg_slave(uint8_t reg, uint8_t val)
{
uint8_t status;
SPI_MasterSSLow(&PORTC, PIN4_bm);
status = SPI_MasterTransceiveByte(&spiMasterC, reg);
SPI_MasterTransceiveByte(&spiMasterC, val);
SPI_MasterSSHigh(&PORTC, PIN4_bm);
return status;
}
void Init_L3G4200DH(void)
{
unsigned char write_register=0;
//CTRL_REG1
//DR1 DR0 BW1 BW0 PD Zen Xen Yen
//0 0 1 1 1 1 1 1
//ODR=100Hz
write_register=0x3f;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x20);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
// spiSendByte(0x20);
// spiSendByte(write_register);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG2
//0 0 HPM1 HPM1 HPCF3 HPCF2 HPCF1 HPCF0
//0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x21);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG3
//I1_Int1 I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty
// 0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x22);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG4
//BDU BLE FS1 FS0 - ST1 ST0 SIM
// 1 0 0 0 0 0 0 0
write_register=0x80;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x23);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG5
//BOOT FIFO_EN - HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0
// 0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x24);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN1_bm);
}
//__________________________________________________________________________________________________
void anibike_dl_master_send_address ( uint8_t address )
{
uint8_t header;
header = DL_SET_ADDRESS|1;
anibike_dl_master_end_transactions
DELAY120NS
DELAY120NS
anibike_dl_master_start_transactions
SPI_MasterTransceiveByte(&spiMasterC, header);
SPI_MasterTransceiveByte(&spiMasterC, address );
anibike_dl_master_end_transactions
}
uint8_t rf_readbuf_master(uint8_t reg, uint8_t readbuf[TX_PLOAD_WIDTH], uint8_t bytes)
{
uint8_t status;
uint16_t i;
SPI_MasterSSLow(&PORTF, PIN4_bm);
status = SPI_MasterTransceiveByte(&spiMasterF, reg);
for (i=0; i<bytes; i++)
{
readbuf[i] = SPI_MasterTransceiveByte(&spiMasterF, 0xff);
}
SPI_MasterSSHigh(&PORTF, PIN4_bm);
return(status);
}
uint8_t rf_writebuf_slave(uint8_t reg, uint8_t * writebuf, uint8_t bytes)
{
uint8_t status;
uint16_t i;
SPI_MasterSSLow(&PORTC, PIN4_bm);
status = SPI_MasterTransceiveByte(&spiMasterC, reg);
for (i=0; i<bytes; i++)
{
SPI_MasterTransceiveByte(&spiMasterC, writebuf[i]);
}
SPI_MasterSSHigh(&PORTC, PIN4_bm);
return(status);
}
int read_sensor_data(unsigned int *xxl,unsigned int *yxl,unsigned int *zxl){
//int read_sensor_data(int *xxl,int *yxl,int *zxl){
// static unsigned char status=0;
static unsigned char acc_data[6];
//check new data available
/* while((status&=0x0f)==0)
{
PORTB&=~(_BV(PB0));
spiSendByte(0xa7);
status=spiTransferByte(0xFF);
PORTB |= _BV(PB0);
}
*/
//sensor data multiple read
PORTC.OUT = PORTC.OUT & 0xfe;//Pc0을 0으로 만드는거
spiSendByte(0xe8);
SPI_MasterTransceiveByte(&spiMasterC, 0xe8);
SPI_MasterTransceiveByte(&spiMasterC, 0xff);
acc_data[0]=spiTransferByte(0xFF);
acc_data[1]=spiTransferByte(0xFF);
acc_data[2]=spiTransferByte(0xFF);
acc_data[3]=spiTransferByte(0xFF);
acc_data[4]=spiTransferByte(0xFF);
acc_data[5]=spiTransferByte(0xFF);
PORTC.OUT = PORTC.OUT | 0x01;//pc1을 1로 만드는거
acc_data[1]=acc_data[1]+0x80;
acc_data[3]=acc_data[3]+0x80;
acc_data[5]=acc_data[5]+0x80;
*xxl= (unsigned int)acc_data[1]*256+acc_data[0];
*yxl= (unsigned int)acc_data[3]*256+acc_data[2];
*zxl= (unsigned int)acc_data[5]*256+acc_data[4];
// *xxl= (int)acc_data[1]*256+acc_data[0];
// *yxl= (int)acc_data[3]*256+acc_data[2];
// *zxl= (int)acc_data[5]*256+acc_data[4];
return 0;
}
uint8_t rf_readreg_slave(uint8_t reg)
{
uint8_t val;
SPI_MasterSSHigh(&PORTC, PIN4_bm);
delay_us(20);
SPI_MasterSSLow(&PORTC, PIN4_bm);
delay_us(20);
SPI_MasterTransceiveByte(&spiMasterC, reg);
val = SPI_MasterTransceiveByte(&spiMasterC, 0xff);
SPI_MasterSSHigh(&PORTC, PIN4_bm);
return val;
}
void Init_LIS331DLH(void)
{
unsigned char write_register=0;
//CTRL_REG1
//PM2 PM1 PM0 DR1 DR0 Zen Yen Xen
//0 0 1 0 1 1 1 1
//ODR=100Hz
write_register=0x2f;
// write_register=DR
SPI_MasterSSLow(ssPort, PIN0_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x20);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN0_bm);
//CTRL_REG2
//BOOT HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0
//0 0 0 0 0 0 00
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN0_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x21);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN0_bm);
//CTRL_REG3
//IHL PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0
//0 0 0 0 0 0 1 0
write_register=0x02;
SPI_MasterSSLow(ssPort, PIN0_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x22);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN0_bm);
//CTRL_REG4
//BDU BLE FS1 FS0 STsign 0 ST SIM
//1 0 0 0 0 0 0 0
write_register=0x80;
SPI_MasterSSLow(ssPort, PIN0_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x23);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN0_bm);
//CTRL_REG5
//0 0 0 0 0 0 TurnOn1 TurnOn0
//0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN0_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x24);
SPI_MasterTransceiveByte(&spiMasterC, write_register);
SPI_MasterSSHigh(ssPort, PIN0_bm);
}
//__________________________________________________________________________________________________
void anibike_dl_master_set_cal_values ( uint16_t r, uint16_t g, uint16_t b )
{
uint8_t header;
header = DL_SET_CAL_VALUES|6;
anibike_dl_master_end_transactions
DELAY120NS
DELAY120NS
anibike_dl_master_start_transactions
SPI_MasterTransceiveByte(&spiMasterC, header);
SPI_MasterTransceiveByte(&spiMasterC, r&0xFF); //LSB
SPI_MasterTransceiveByte(&spiMasterC, (r>>8)&0xFF); //MSB
SPI_MasterTransceiveByte(&spiMasterC, g&0xFF); //LSB
SPI_MasterTransceiveByte(&spiMasterC, (g>>8)&0xFF); //MSB
SPI_MasterTransceiveByte(&spiMasterC, b&0xFF); //LSB
SPI_MasterTransceiveByte(&spiMasterC, (b>>8)&0xFF); //MSB
anibike_dl_master_end_transactions
}
//__________________________________________________________________________________________________
void anibike_dl_master_send_data ( uint8_t *data, uint8_t length ) // length smaller then 32
{
uint8_t header;
header = DL_CONTINUE_DATA_BATCH | length;
//SPI_MasterSSLow (&DATALINK_PORT, DATALINK_CS_PIN);
SPI_MasterTransceiveByte(&spiMasterC, (uint8_t)(header));
DELAY120NS
while (length--)
{
//NOP;NOP;NOP;
uint8_t d = *data++;
SPI_MasterTransceiveByte(&spiMasterC, d);
}
//SPI_MasterSSHigh (&DATALINK_PORT, DATALINK_CS_PIN);
}
//__________________________________________________________________________________________________
void anibike_dl_master_send_light_leds_debug ( uint8_t row, uint8_t rgb, uint8_t val )
{
uint8_t header;
header = DL_LIGHT_LEDS_DEBUG|3;
anibike_dl_master_end_transactions
DELAY120NS
DELAY120NS
anibike_dl_master_start_transactions
//printf_P(PSTR("sending %d %d %d %d\r\n"), (uint8_t)(header), row, rgb, val);
SPI_MasterTransceiveByte(&spiMasterC, header);
SPI_MasterTransceiveByte(&spiMasterC, row);
SPI_MasterTransceiveByte(&spiMasterC, rgb);
SPI_MasterTransceiveByte(&spiMasterC, val);
SPI_MasterSSHigh (&DATALINK_PORT, DATALINK_CS_PIN);
}
uint8_t Check_ACK_slave(uint8_t clear)
{
//while(ioport_get_value(nrf24l01S_IRQ));//IRQ is active low, so if there is no event, in the loop
//sta = SPI_MasterTransceiveByte(&spiMasterC, 0xff);
sta = rf_readreg_slave(STATUSREG);
SPI_MasterTransceiveByte(&spiMasterC, FLUSH_TX);
rf_writereg_slave(WRITE_REG + STATUSREG, sta);
SPI_MasterTransceiveByte(&spiMasterC, FLUSH_TX);
//IRQ = 1;
//ioport_configure_pin(nrf24l01S_IRQ, IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH);
//ioport_set_pin_high(nrf24l01S_IRQ);
//ioport_configure_pin(nrf24l01S_IRQ, IOPORT_DIR_INPUT);
if (TX_DS)
return 0x00;
else
return 0xff;
}
//__________________________________________________________________________________________________
void anibike_dl_master_go_to_sleep ( void )
{
uint8_t header;
header = DL_GO_TO_SLEEP;
anibike_dl_master_end_transactions
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
anibike_dl_master_start_transactions
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
DELAY120NS
SPI_MasterTransceiveByte(&spiMasterC, header);
anibike_dl_master_end_transactions
}
uint8_t rf_SPI_RW_slave(uint8_t val)
{
return SPI_MasterTransceiveByte(&spiMasterC, val);
}
uint8_t rf_SPI_RW_master(uint8_t val)
{
return SPI_MasterTransceiveByte(&spiMasterF, val);
}
//__________________________________________________________________________________________________
void anibike_dl_master_send_timing_sync ( void )
{
uint8_t header;
header = DL_NEW_TIMING_SYNC;
SPI_MasterTransceiveByte(&spiMasterC, header);
}
/*
void Init_L3G4200DH(void)
{
unsigned char write_register=0;
//CTRL_REG1
//DR1 DR0 BW1 BW0 PD Zen Xen Yen
//0 0 1 1 1 1 1 1
//ODR=100Hz
write_register=0x3f;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x20);
SPI_MasterTransceiveByte(&spiMasterC, 0x3f);
// spiSendByte(0x20);
// spiSendByte(write_register);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG2
//0 0 HPM1 HPM1 HPCF3 HPCF2 HPCF1 HPCF0
//0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x21);
SPI_MasterTransceiveByte(&spiMasterC, 0x00);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG3
//I1_Int1 I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty
// 0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x22);
SPI_MasterTransceiveByte(&spiMasterC, 0x00);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG4
//BDU BLE FS1 FS0 - ST1 ST0 SIM
// 1 0 0 0 0 0 0 0
write_register=0x80;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x23);
SPI_MasterTransceiveByte(&spiMasterC, 0x80);
SPI_MasterSSHigh(ssPort, PIN1_bm);
//CTRL_REG5
//BOOT FIFO_EN - HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0
// 0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN1_bm);
SPI_MasterTransceiveByte(&spiMasterC, 0x24);
SPI_MasterTransceiveByte(&spiMasterC, 0x00);
SPI_MasterSSHigh(ssPort, PIN1_bm);
}
*/
void Init_LIS3DH(void)
{
unsigned char write_register=0;
//CTRL_REG1
//ODR3 ODR2 ODR1 ODR0 LPen Zen Yen Xen
// 0 1 0 1 0 1 1 1
//ODR=100Hz
write_register=0x57;
// write_register=DR
SPI_MasterSSLow(ssPort, PIN0_bm);
_delay_us(10);
SPI_MasterTransceiveByte(&spiMasterD, 0x20);
SPI_MasterTransceiveByte(&spiMasterD, write_register);
_delay_us(10);
SPI_MasterSSHigh(ssPort, PIN0_bm);
_delay_us(10);
//CTRL_REG2
//HPM1 HPM0 HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1
// 0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN0_bm);
_delay_us(10);
SPI_MasterTransceiveByte(&spiMasterD, 0x21);
SPI_MasterTransceiveByte(&spiMasterD, write_register);
_delay_us(10);
SPI_MasterSSHigh(ssPort, PIN0_bm);
_delay_us(10);
//CTRL_REG3
//I1_CLICK I1_AOI1 I1_AOI2 I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN --
// 0 0 0 0 0 0 1 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN0_bm);
_delay_us(10);
SPI_MasterTransceiveByte(&spiMasterD, 0x22);
SPI_MasterTransceiveByte(&spiMasterD, write_register);
_delay_us(10);
SPI_MasterSSHigh(ssPort, PIN0_bm);
_delay_us(10);
//CTRL_REG4
//BDU BLE FS1 FS0 HR ST1 ST0 SIM
//1 0 0 0 1 0 0 0
write_register=0x88;
SPI_MasterSSLow(ssPort, PIN0_bm);
_delay_us(10);
SPI_MasterTransceiveByte(&spiMasterD, 0x23);
SPI_MasterTransceiveByte(&spiMasterD, write_register);
_delay_us(10);
SPI_MasterSSHigh(ssPort, PIN0_bm);
_delay_us(10);
//CTRL_REG5
//BOOT FIFO_EN -- -- LIR_INT1 D4D_INT1 0 0
//0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN0_bm);
_delay_us(10);
SPI_MasterTransceiveByte(&spiMasterD, 0x24);
SPI_MasterTransceiveByte(&spiMasterD, write_register);
_delay_us(10);
SPI_MasterSSHigh(ssPort, PIN0_bm);
//CTRL_REG6
//I2_CLICKen I2_INT1 0 BOOT_I1 0 - - H_LACTIVE -
// 0 0 0 0 0 0 0 0
write_register=0x00;
SPI_MasterSSLow(ssPort, PIN0_bm);
_delay_us(10);
SPI_MasterTransceiveByte(&spiMasterD, 0x25);
SPI_MasterTransceiveByte(&spiMasterD, write_register);
_delay_us(10);
SPI_MasterSSHigh(ssPort, PIN0_bm);
write_register=0xC0;
SPI_MasterSSLow(ssPort, PIN0_bm);
_delay_us(10);
SPI_MasterTransceiveByte(&spiMasterD, 0x1F);
SPI_MasterTransceiveByte(&spiMasterD, write_register);
_delay_us(10);
SPI_MasterSSHigh(ssPort, PIN0_bm);
}
/*! \brief Test function.
*
* This function tests the SPI master and slave drivers in polled operation,
* with a master (on port C) communicating with a slave (on port D).
*
* Hardware setup:
*
* - Connect PC4 to PD4 (SS)
* - Connect PC5 to PD5 (MOSI)
* - Connect PC6 to PD6 (MISO)
* - Connect PC7 to PD7 (SCK)
*
* The drivers are tested in two phases:
*
* 1: Data is transmitted on byte at a time from the master to the slave.
* The slave increments the received data and sends it back. The master reads
* the data from the slave and verifies that it equals the data sent + 1.
*
* 2: Data is transmitted 4 bytes at a time to the slave. As the master sends
* a byte to the slave, the preceding byte is sent back to the master.
* When all bytes have been sent, it is verified that the last 3 bytes
* received at the master, equal the first 3 bytes sent.
*
* The variable, 'success', will be non-zero when the function reaches the
* infinite for-loop if the test was successful.
*/
int main(void)
{
/* Init SS pin as output with wired AND and pull-up. */
PORTC.DIRSET = PIN4_bm;
PORTC.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc;
/* Set SS output to high. (No slave addressed). */
PORTC.OUTSET = PIN4_bm;
/* Instantiate pointer to ssPort. */
PORT_t *ssPort = &PORTC;
/* Initialize SPI master on port C. */
SPI_MasterInit(&spiMasterC,
&SPIC,
&PORTC,
false,
SPI_MODE_0_gc,
SPI_INTLVL_LO_gc,
false,
SPI_PRESCALER_DIV4_gc);
/* Initialize SPI slave on port D. */
SPI_SlaveInit(&spiSlaveD,
&SPID,
&PORTD,
false,
SPI_MODE_0_gc,
SPI_INTLVL_LO_gc);
/* PHASE 1: Transceive individual bytes. */
/* MASTER: Pull SS line low. This has to be done since
* SPI_MasterTransceiveByte() does not control the SS line(s). */
SPI_MasterSSLow(ssPort, PIN4_bm);
for(uint8_t i = 0; i < NUM_BYTES; i++) {
/* MASTER: Transmit data from master to slave. */
SPI_MasterTransceiveByte(&spiMasterC, masterSendData[i]);
/* SLAVE: Wait for data to be available. */
while (SPI_SlaveDataAvailable(&spiSlaveD) == false) {
}
/* SLAVE: Get the byte received. */
uint8_t slaveByte = SPI_SlaveReadByte(&spiSlaveD);
/* SLAVE: Increment received byte and send back. */
slaveByte++;
SPI_SlaveWriteByte(&spiSlaveD, slaveByte);
/* MASTER: Transmit dummy data to shift data from slave to master. */
uint8_t masterReceivedByte = SPI_MasterTransceiveByte(&spiMasterC, 0x00);
/* MASTER: Check if the correct value was received. */
if (masterReceivedByte != (masterSendData[i] + 1) ) {
success = false;
}
}
/* MASTER: Release SS to slave. */
SPI_MasterSSHigh(ssPort, PIN4_bm);
/* PHASE 2: Transceive data packet. */
/* Create data packet (SS to slave by PC4). */
SPI_MasterCreateDataPacket(&dataPacket,
masterSendData,
masterReceivedData,
NUM_BYTES,
&PORTC,
PIN4_bm);
/* Transceive packet. */
SPI_MasterTransceivePacket(&spiMasterC, &dataPacket);
/* Check that correct data was received. Assume success at first. */
for (uint8_t i = 0; i < NUM_BYTES - 1; i++) {
if (masterReceivedData[i + 1] != masterSendData[i]) {
success = false;
}
}
while(true) {
nop();
}
}
