void HAL::spiSendBlock(uint8_t token, const uint8_t* buf)
{
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
SPI0->SPI_RDR;
for (int i=0; i<511; i++)
{
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
SPI0->SPI_RDR;
}
spiSend(buf[511]);
}
/**
* \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
* peripheral select, the npcs value is meaningless. Otherwise, it identifies
* the component which shall be addressed.
*
* \param spi Pointer to an Spi instance.
* \param npcs Chip select of the component to address (0, 1, 2 or 3).
* \param data Word of data to send.
*/
void SPI_Write(Spi *spi, uint32_t npcs, uint16_t data)
{
/* Send data */
while ((spi->SPI_SR & SPI_SR_TXEMPTY) == 0);
spi->SPI_TDR = data | SPI_PCS(npcs);
while ((spi->SPI_SR & SPI_SR_TDRE) == 0);
}
/**
* \brief Initialization of the SPI for communication with ADS7843 component.
*/
extern void ADS7843_Initialize( void )
{
volatile uint32_t uDummy;
/* Configure pins */
PIO_Configure(pinsSPI, PIO_LISTSIZE(pinsSPI));
PIO_Configure(pinBusy, PIO_LISTSIZE(pinBusy));
SPI_Configure(BOARD_TSC_SPI_BASE,
BOARD_TSC_SPI_ID,
SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_PCS(BOARD_TSC_NPCS) /* Value of the SPI configuration register. */
);
SPI_ConfigureNPCS(BOARD_TSC_SPI_BASE, BOARD_TSC_NPCS,
SPI_CSR_NCPHA | SPI_CSR_DLYBS(DELAY_BEFORE_SPCK) |
SPI_CSR_DLYBCT(DELAY_BETWEEN_CONS_COM) | SPI_CSR_SCBR(0xC8) );
SPI_Enable(BOARD_TSC_SPI_BASE);
for (uDummy=0; uDummy<100000; uDummy++);
uDummy = REG_SPI_SR;
uDummy = REG_SPI_RDR;
SendCommand(CMD_ENABLE_PENIRQ);
}
/**
* \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
* peripheral select, the npcs value is meaningless. Otherwise, it identifies
* the component which shall be addressed.
*
* \param spi Pointer to an Spi instance.
* \param npcs Chip select of the component to address (0, 1, 2 or 3).
* \param data Word of data to send.
*/
extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData )
{
/* Send data */
while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;
spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;
while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ;
}
// =============================================================================
// 功能：写SPI发送寄存器，轮询方式,被__SPI_TxRxPoll调用
// 参数：Reg,寄存器基址，dwNpcs,片选；wData，写数据
// 返回：无
// =============================================================================
static void __SPI_Write( tagSpiReg * Reg, uint32_t dwNpcs, uint16_t wData )
{
/* Send data */
while ( (Reg->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;
Reg->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;
while ( (Reg->SPI_SR & SPI_SR_TDRE) == 0 ) ;
}
/**
* \brief ILI9488 Hardware Initialization for SPI/SMC LCD.
*/
static void _ILI9488_Spi_HW_Initialize(void)
{
/* Pin configurations */
PIO_Configure(&lcd_spi_reset_pin, 1);
PIO_Configure(&lcd_spi_cds_pin, 1);
PIO_Configure(lcd_pins, PIO_LISTSIZE(lcd_pins));
PIO_Configure(&lcd_spi_pwm_pin, 1);
/* Enable PWM peripheral clock */
PMC_EnablePeripheral(ID_PWM0);
PMC_EnablePeripheral(ID_SPI0);
/* Set clock A and clock B */
// set for 14.11 KHz for CABC control
//mode = PWM_CLK_PREB(0x0A) | (PWM_CLK_DIVB(110)) |
//PWM_CLK_PREA(0x0A) | (PWM_CLK_DIVA(110));
PWMC_ConfigureClocks(PWM0, 14200, 0, BOARD_MCK);
/* Configure PWM channel 1 for LED0 */
PWMC_DisableChannel(PWM0, CHANNEL_PWM_LCD);
PWMC_ConfigureChannel(PWM0, CHANNEL_PWM_LCD, PWM_CMR_CPRE_CLKA, 0,
PWM_CMR_CPOL);
PWMC_SetPeriod(PWM0, CHANNEL_PWM_LCD, 16);
PWMC_SetDutyCycle(PWM0, CHANNEL_PWM_LCD, 8);
PWMC_EnableChannel(PWM0, CHANNEL_PWM_LCD);
SPI_Configure(ILI9488_SPI, ID_SPI0, (SPI_MR_MSTR | SPI_MR_MODFDIS
| SPI_PCS(SMC_EBI_LCD_CS)));
SPI_ConfigureNPCS(ILI9488_SPI,
SMC_EBI_LCD_CS,
SPI_CSR_CPOL | SPI_CSR_BITS_8_BIT | SPI_DLYBS(6, BOARD_MCK)
| SPI_DLYBCT(100, BOARD_MCK) | SPI_SCBR(20000000, BOARD_MCK));
SPI_Enable(ILI9488_SPI);
}
static void ILI9488_InitInterface(void)
{
PIO_Configure(ILI9488_Reset, PIO_LISTSIZE(ILI9488_Reset));
PIO_Configure(spi_pins, PIO_LISTSIZE(spi_pins));
PIO_Configure(ILI9488_Pwm, PIO_LISTSIZE(ILI9488_Pwm));
/* Enable PWM peripheral clock */
PMC_EnablePeripheral(ID_PWM0);
/* Set clock A and clock B */
// set for 14.11 KHz for CABC control
// mode = PWM_CLK_PREB(0x0A) | (PWM_CLK_DIVB(110)) |
// PWM_CLK_PREA(0x0A) | (PWM_CLK_DIVA(110));
PWMC_ConfigureClocks(PWM0, 14200, 0, BOARD_MCK);
/* Configure PWM channel 1 for LED0 */
PWMC_DisableChannel(PWM0, CHANNEL_PWM_LCD);
PWMC_ConfigureChannel(PWM0, CHANNEL_PWM_LCD, PWM_CMR_CPRE_CLKA,0,PWM_CMR_CPOL);
PWMC_SetPeriod(PWM0, CHANNEL_PWM_LCD, 16);
PWMC_SetDutyCycle(PWM0, CHANNEL_PWM_LCD, 8);
PWMC_EnableChannel(PWM0, CHANNEL_PWM_LCD);
SPI_Configure(ILI9488, ILI9488_ID, (SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_PCS( ILI9488_cs )));
SPI_ConfigureNPCS( ILI9488, ILI9488_cs,
SPI_CSR_CPOL | SPI_CSR_BITS_9_BIT |
SPI_DLYBS(100, BOARD_MCK) | SPI_DLYBCT(100, BOARD_MCK) |
SPI_SCBR( 35000000, BOARD_MCK) ) ;
SPI_Enable(ILI9488);
}
// Write single byte to SPI
void HAL::spiSend(byte b) {
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// write byte with address and end transmission flag
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// clear status
SPI0->SPI_RDR;
}
// Read single byte from SPI
uint8_t HAL::spiReceive()
{
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// write dummy byte with address and end transmission flag
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// get byte from receive register
return SPI0->SPI_RDR;
}
void HAL::spiSend(const uint8_t* buf , size_t n)
{
if (n == 0) return;
for (int i=0; i<n-1; i++)
{
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
SPI0->SPI_RDR;
}
spiSend(buf[n-1]);
}
/**
* \brief Configures spi in slave mode.
*/
static void _ConfigureSpiSlave( void )
{
/* Configure SPI slave mode */
SPI_Configure(SPI, ID_SPI, SPI_PCS(0));
NVIC_ClearPendingIRQ(SPI_IRQn);
NVIC_SetPriority(SPI_IRQn ,1);
NVIC_EnableIRQ(SPI_IRQn);
SPI_DisableIt(SPI, 0xffffffff);
SPI_ConfigureNPCS(SPI, 0, 0);
}
// Read from SPI into buffer
void HAL::spiReadBlock(uint8_t*buf,uint16_t nbyte)
{
if (nbyte-- == 0) return;
for (int i=0; i<nbyte; i++)
{
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
buf[i] = SPI0->SPI_RDR;
}
buf[nbyte] = spiReceive();
}
uint8_t hwspi0_transfer(uint8_t data){
uint32_t ch = 0;
uint32_t d = data | SPI_PCS(0);
/*if (_mode == SPI_LAST)
d |= SPI_TDR_LASTXFER;*/
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = d;
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
d = SPI0->SPI_RDR;
return d & 0xff;
}
void HAL::spiSend(uint32_t chan, byte b)
{
uint8_t dummy_read = 0;
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// write byte with address and end transmission flag
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(chan) | SPI_TDR_LASTXFER;
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// clear status
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
dummy_read = SPI0->SPI_RDR;
}
//------------------------------------------------------------------------------
// initialize SPI controller
void SdSpi::init(uint8_t sckDivisor) {
uint8_t scbr = sckDivisor;
Spi* pSpi = SPI0;
// disable SPI
pSpi->SPI_CR = SPI_CR_SPIDIS;
// reset SPI
pSpi->SPI_CR = SPI_CR_SWRST;
// no mode fault detection, set master mode
pSpi->SPI_MR = SPI_PCS(SPI_CHIP_SEL) | SPI_MR_MODFDIS | SPI_MR_MSTR;
// mode 0, 8-bit,
pSpi->SPI_CSR[SPI_CHIP_SEL] = SPI_CSR_SCBR(scbr) | SPI_CSR_NCPHA;
// enable SPI
pSpi->SPI_CR |= SPI_CR_SPIEN;
}
void HAL::spiSend(uint32_t chan , const uint8_t* buf , size_t n)
{
uint8_t dummy_read = 0;
if (n == 0) return;
for (int i = 0; i < n - 1; i++)
{
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(chan);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
dummy_read = SPI0->SPI_RDR;
}
spiSend(chan, buf[n - 1]);
}
/**
* \brief Initialize SPI as master
*/
static void SpiMasterInitialize( void )
{
printf( "-I- Configure SPI as master\n\r" ) ;
/* Master mode */
SPI_Configure( SPI_MASTER_BASE, ID_SPI, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_PCS( 0 ) ) ;
SPI_ConfigureNPCS( SPI_MASTER_BASE, 0, SPI_DLYBCT( 100000, BOARD_MCK ) | SPI_DLYBS(100000, BOARD_MCK) | SPI_SCBR( spiClock, BOARD_MCK) ) ;
/* Disable the RX and TX PDC transfer requests */
SPI_PdcDisableTx( SPI_MASTER_BASE ) ;
SPI_PdcDisableRx( SPI_MASTER_BASE ) ;
/* Enables a SPI peripheral. */
SPI_Enable( SPI_MASTER_BASE ) ;
}
uint8_t HAL::spiReceive(uint32_t chan)
{
uint8_t spirec_tmp;
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
spirec_tmp = SPI0->SPI_RDR;
// write dummy byte with address and end transmission flag
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// get byte from receive register
return SPI0->SPI_RDR;
}
/**
* \brief Configures spi in master mode.
*/
static void _ConfigureSpiMaster(void)
{
/* Configure SPI master mode */
SPI_Configure(SPI, ID_SPI, (SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_PCS(1)));
NVIC_ClearPendingIRQ(SPI_IRQn);
NVIC_SetPriority(SPI_IRQn ,1);
NVIC_EnableIRQ(SPI_IRQn);
SPI_DisableIt(SPI, 0xffffffff);
SPI_ConfigureNPCS(SPI, 1,
SPI_DLYBCT( 100, BOARD_MCK ) |
SPI_DLYBS(100, BOARD_MCK) |
SPI_SCBR( spiClock, BOARD_MCK) |
SPI_CSR_BITS_8_BIT);
}
//------------------------------------------------------------------------------
// initialize SPI controller
void SdSpiAltDriver::activate() {
SPI.beginTransaction(m_spiSettings);
Spi* pSpi = SPI0;
// Save the divisor
uint32_t scbr = pSpi->SPI_CSR[SPI_CHIP_SEL] & 0XFF00;
// Disable SPI
pSpi->SPI_CR = SPI_CR_SPIDIS;
// reset SPI
pSpi->SPI_CR = SPI_CR_SWRST;
// no mode fault detection, set master mode
pSpi->SPI_MR = SPI_PCS(SPI_CHIP_SEL) | SPI_MR_MODFDIS | SPI_MR_MSTR;
// mode 0, 8-bit,
pSpi->SPI_CSR[SPI_CHIP_SEL] = scbr | SPI_CSR_CSAAT | SPI_CSR_NCPHA;
// enable SPI
pSpi->SPI_CR |= SPI_CR_SPIEN;
}
/**
* @brief Asserts the slave select signal and prepares for transfers.
*
* @param[in] spip pointer to the @p SPIDriver object
*
* @notapi
*/
void spi_lld_select(SPIDriver *spip) {
/**
* NOTE: This should only be called in master mode.
*/
uint16_t pad = spip->config->npcs;
/* Disable write protection */
spiDisableWP(spip->spi);
spip->spi->SPI_MR &= ~SPI_MR_PCS_Msk;
spip->spi->SPI_MR |= SPI_PCS(pad);
/* Enable write protection */
spiEnableWP(spip->spi);
}
void spi_stack_master_init(void) {
Pin spi_master_pins[] = {PINS_SPI};
PIO_Configure(spi_master_pins, PIO_LISTSIZE(spi_master_pins));
#ifndef CONSOLE_USART_USE_UART1
if(master_get_hardware_version() > 10) {
Pin spi_select_7_20 = PIN_SPI_SELECT_MASTER_7_20;
memcpy(&spi_select_master[7], &spi_select_7_20, sizeof(Pin));
} else {
Pin spi_select_7_10 = PIN_SPI_SELECT_MASTER_7_10;
memcpy(&spi_select_master[7], &spi_select_7_10, sizeof(Pin));
}
PIO_Configure(spi_select_master, 8);
#else
PIO_Configure(spi_select_master, 7);
#endif
// Master mode configuration
SPI_Configure(SPI,
ID_SPI,
// Master mode
SPI_MR_MSTR |
// Mode fault detection disabled
SPI_MR_MODFDIS |
// Wait until receive register empty before read
SPI_MR_WDRBT |
// Chip select number
SPI_PCS(0) |
// Delay between chip selects
SPI_DLYBCS(SPI_DELAY_BETWEEN_CHIP_SELECT, BOARD_MCK));
// Configure slave select
SPI_ConfigureNPCS(SPI,
// slave select num
0,
// Delay between consecutive transfers
SPI_DLYBCT(SPI_DELAY_BETWEEN_TRANSFER, BOARD_MCK) |
// Delay before first SPCK
SPI_DLYBS(SPI_DELAY_BEFORE_FIRST_SPI_CLOCK, BOARD_MCK) |
// SPI baud rate
SPI_SCBR(SPI_CLOCK, BOARD_MCK));
// Enable SPI peripheral.
SPI_Enable(SPI);
}
//------------------------------------------------------------------------------
// initialize SPI controller
void spiInit(uint8_t bitOrder, uint8_t spiMode, uint8_t spiClockDivider) {
uint8_t scbr;
Spi* pSpi = SPI0;
scbr = spiClockDivider;
// disable SPI
pSpi->SPI_CR = SPI_CR_SPIDIS;
// reset SPI
pSpi->SPI_CR = SPI_CR_SWRST;
// no mode fault detection, set master mode
pSpi->SPI_MR = SPI_PCS(SPI_CHIP_SEL) | SPI_MR_MODFDIS | SPI_MR_MSTR;
if (spiMode == SPI_MODE0) { // SPI_MODE0, SPI_MODE1; other modes currently not supported.
// mode 0, 8-bit,
pSpi->SPI_CSR[SPI_CHIP_SEL] = SPI_CSR_SCBR(scbr) | SPI_CSR_NCPHA;
} else {
// mode 1, 8-bit,
pSpi->SPI_CSR[SPI_CHIP_SEL] = SPI_CSR_SCBR(scbr);
}
// enable SPI
pSpi->SPI_CR |= SPI_CR_SPIEN;
}
// Initialises the SPI controller on the at91.
void Init_SPI(void)
{
SPI_Configure(AT91C_BASE_SPI0,
AT91C_ID_SPI0,
AT91C_SPI_MSTR |
AT91C_SPI_PS_FIXED |
AT91C_SPI_MODFDIS |
SPI_PCS(0)
);
//Configure SPI Chip Select Register.
SPI_ConfigureNPCS(AT91C_BASE_SPI0,
0, // NPCS0
AT91C_SPI_NCPHA | // Mode 0 (CPOL=0,CPHA=0)
(128 << 8) | // SCBR: SPCK=MCK/SCBR //8 or 64
(0 << 16) | // DLYBS: Delay from NPCS to SPCK in MCK cycles
(0 << 24) | // DLYBCT: Delay between consec xfers
AT91C_SPI_BITS_8 // 8-data bits
);
SPI_Enable(AT91C_BASE_SPI0);
}
byte SPIClass::transfer(byte _pin, uint8_t _data, SPITransferMode _mode) {
uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
// Reverse bit order
if (bitOrder[ch] == LSBFIRST)
_data = __REV(__RBIT(_data));
uint32_t d = _data | SPI_PCS(ch);
if (_mode == SPI_LAST)
d |= SPI_TDR_LASTXFER;
// SPI_Write(spi, _channel, _data);
while ((spi->SPI_SR & SPI_SR_TDRE) == 0)
;
spi->SPI_TDR = d;
// return SPI_Read(spi);
while ((spi->SPI_SR & SPI_SR_RDRF) == 0)
;
d = spi->SPI_RDR;
// Reverse bit order
if (bitOrder[ch] == LSBFIRST)
d = __REV(__RBIT(d));
return d & 0xFF;
}
/**
* \brief usart_spi Application entry point.
*
* \return Unused (ANSI-C compatibility).
*/
extern int main(void)
{
uint8_t ucKey, i;
/* Disable watchdog */
WDT_Disable(WDT);
SCB_EnableICache();
SCB_EnableDCache();
/* Configure systick for 1 ms. */
TimeTick_Configure();
/* Output example information */
printf("-- USART SPI Example %s --\n\r", SOFTPACK_VERSION);
printf("-- %s\n\r", BOARD_NAME);
printf("-- Compiled: %s %s With %s--\n\r", __DATE__, __TIME__, COMPILER_NAME);
/* Display menu */
_DisplayMainmenu();
while (1) {
ucKey = DBG_GetChar();
switch (ucKey) {
/*usart as spi master*/
case 'm':
case 'M':
/* Configure pins*/
PIO_Configure(pins1, PIO_LISTSIZE(pins1));
/* Configure USART as SPI master */
_ConfigureUsartAsSpiMaster();
/* Configure SPi slave */
_ConfigureSpiSlave();
printf("-I- Configure USART as spi master ...\n\r");
SPI_EnableIt(SPI, SPI_IER_RDRF);
SPI_Enable(SPI);
USART_EnableIt(USART, UART_IER_RXRDY);
for (i = 0; (pTxBuffer1[i]!='\0' && pTxBuffer2[i]!='\0'); i++) {
while ((SPI->SPI_SR & SPI_SR_TXEMPTY) == 0);
SPI->SPI_TDR = ((uint16_t)pTxBuffer2[i]) | SPI_PCS( 0 );
USART_Write( USART, pTxBuffer1[i], 0);
}
break;
/*usart as spi slave*/
case 's':
case 'S':
printf("-I- Configure USART as spi slave...\n\r");
/* Configure pins*/
PIO_Configure(pins2, PIO_LISTSIZE(pins2));
/* Configure USART as SPI slave */
_ConfigureUsartAsSpiSlave();
/* Configure SPI master */
_ConfigureSpiMaster();
USART_EnableIt(USART, UART_IER_RXRDY);
SPI_EnableIt(SPI, SPI_IER_RDRF);
SPI_Enable(SPI);
for (i = 0; (pTxBuffer1[i]!='\0' && pTxBuffer2[i]!='\0'); i++) {
USART_Write(USART, (uint16_t)pTxBuffer2[i], 0);
SPI_Write( SPI, 1, (uint16_t)pTxBuffer1[i]);
}
break;
case 'h':
case 'H':
_DisplayMainmenu();
break;
}
}
}
/**
* \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
* peripheral select, the npcs value is meaningless. Otherwise, it identifies
* the component which shall be addressed.
*
* \param spi Pointer to an Spi instance.
* \param npcs Chip select of the component to address (0, 1, 2 or 3).
* \param data Word of data to send.
*/
extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData )
{
/* Send data */
spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;
}
void spi_stack_master_init(void) {
// Set starting sequence number to something that slave does not expect
// (default for slave is 0)
//spi_stack_master_seq = 1;
for(uint8_t i = 0; i < SPI_ADDRESS_MAX; i++) {
slave_status[i] = SLAVE_STATUS_ABSENT;
}
Pin spi_master_pins[] = {PINS_SPI};
PIO_Configure(spi_master_pins, PIO_LISTSIZE(spi_master_pins));
#ifndef CONSOLE_USART_USE_UART1
if(master_get_hardware_version() > 10) {
Pin spi_select_7_20 = PIN_SPI_SELECT_MASTER_7_20;
memcpy(&spi_select_master[7], &spi_select_7_20, sizeof(Pin));
} else {
Pin spi_select_7_10 = PIN_SPI_SELECT_MASTER_7_10;
memcpy(&spi_select_master[7], &spi_select_7_10, sizeof(Pin));
}
PIO_Configure(spi_select_master, 8);
#else
PIO_Configure(spi_select_master, 7);
#endif
// Configure SPI interrupts for Master
NVIC_DisableIRQ(SPI_IRQn);
NVIC_ClearPendingIRQ(SPI_IRQn);
NVIC_SetPriority(SPI_IRQn, PRIORITY_STACK_MASTER_SPI);
NVIC_EnableIRQ(SPI_IRQn);
// SPI reset
SPI->SPI_CR = SPI_CR_SWRST;
// Master mode configuration
SPI_Configure(SPI,
ID_SPI,
// Master mode
SPI_MR_MSTR |
// Mode fault detection disabled
SPI_MR_MODFDIS |
// Wait until receive register empty before read
SPI_MR_WDRBT |
// Chip select number
SPI_PCS(0) |
// Delay between chip selects
SPI_DLYBCS(SPI_DELAY_BETWEEN_CHIP_SELECT, BOARD_MCK));
// Configure slave select
SPI_ConfigureNPCS(SPI,
// slave select num
0,
// Delay between consecutive transfers
SPI_DLYBCT(SPI_DELAY_BETWEEN_TRANSFER, BOARD_MCK) |
// Delay before first SPCK
SPI_DLYBS(SPI_DELAY_BEFORE_FIRST_SPI_CLOCK, BOARD_MCK) |
// SPI baud rate
SPI_SCBR(SPI_CLOCK, BOARD_MCK));
// Disable RX and TX DMA transfer requests
spi_stack_master_disable_dma();
// Enable SPI peripheral.
SPI_Enable(SPI);
spi_stack_master_reset_recv_dma_buffer();
spi_stack_master_reset_send_dma_buffer();
// Call interrupt on end of slave select
SPI_EnableIt(SPI, SPI_IER_ENDRX | SPI_IER_ENDTX);
}
