//-----------------------------------------------------------------//
// Setup DMA
// HCLK = 32 MHz
//-----------------------------------------------------------------//
void HW_DMAInit(void)
{
// Reset all DMA settings
DMA_DeInit();
// Vital for proper DMA IRQ function
// Single requests from ADC?
MDR_DMA->CHNL_REQ_MASK_SET = 0xFFFFFFFF; // Disable all requests
MDR_DMA->CHNL_USEBURST_SET = 0xFFFFFFFF; // disable sreq[]
// MDR32F9Qx false DMA requests workaround
// This must be executed next to clock setup
RST_CLK_PCLKcmd(RST_CLK_PCLK_SSP1 ,ENABLE);
SSP_BRGInit(MDR_SSP1,SSP_HCLKdiv1);
MDR_SSP1->DMACR = 0; // Reset false requests
MDR_SSP2->DMACR = 0;
RST_CLK_PCLKcmd(RST_CLK_PCLK_SSP1 ,DISABLE);
NVIC->ICPR[0] = 0xFFFFFFFF; // Reset all pending interrupts
NVIC->ICER[0] = 0xFFFFFFFF; // Disable all interrupts
my_DMA_GlobalInit();
NVIC_EnableIRQ(DMA_IRQn);
}
//-----------------------------------------------------------------//
// Setup SSP module
// HCLK = 32 MHz
// The information rate is computed using the following formula:
// F_SSPCLK / ( CPSDVR * (1 + SCR) )
// 3.2 MHz
//-----------------------------------------------------------------//
void HW_SSPInit(void)
{
SSP_InitTypeDef sSSP;
SSP_StructInit (&sSSP);
SSP_BRGInit(MDR_SSP2,SSP_HCLKdiv1); // F_SSPCLK = HCLK / 1
sSSP.SSP_SCR = 0x04; // 0 to 255
sSSP.SSP_CPSDVSR = 2; // even 2 to 254
sSSP.SSP_Mode = SSP_ModeMaster;
sSSP.SSP_WordLength = SSP_WordLength9b;
sSSP.SSP_SPH = SSP_SPH_1Edge;
sSSP.SSP_SPO = SSP_SPO_Low;
sSSP.SSP_FRF = SSP_FRF_SPI_Motorola;
sSSP.SSP_HardwareFlowControl = SSP_HardwareFlowControl_SSE;
SSP_Init (MDR_SSP2,&sSSP);
SSP_Cmd(MDR_SSP2, ENABLE);
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2 | RST_CLK_PCLK_DMA),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTF | RST_CLK_PCLK_PORTD), ENABLE);
/* Init NVIC */
SCB->AIRCR = 0x05FA0000 | ((uint32_t)0x500);
SCB->VTOR = 0x08000000;
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Disable all DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTD settings */
PORT_DeInit(MDR_PORTD);
/* Reset PORTF settings */
PORT_DeInit(MDR_PORTF);
/* Configure SSP2 pins: FSS, CLK, RXD, TXD */
/* Configure PORTD pins 2, 3, 5, 6 */
PORT_InitStructure.PORT_Pin = (PORT_Pin_2 | PORT_Pin_3 | PORT_Pin_5);
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_ALTER;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_Pin = (PORT_Pin_6);
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Configure SSP1 pins: FSS, CLK, RXD, TXD */
/* Configure PORTF pins 0, 1, 2, 3 */
PORT_InitStructure.PORT_Pin = (PORT_Pin_3);
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTF, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = (PORT_Pin_0 | PORT_Pin_1 | PORT_Pin_2);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTF, &PORT_InitStructure);
/* Init RAM */
Init_RAM (DstBuf1, BufferSize);
Init_RAM (SrcBuf1, BufferSize);
Init_RAM (DstBuf2, BufferSize);
Init_RAM (SrcBuf2, BufferSize);
/* Reset all SSP settings */
SSP_DeInit(MDR_SSP1);
SSP_DeInit(MDR_SSP2);
SSP_BRGInit(MDR_SSP1,SSP_HCLKdiv16);
SSP_BRGInit(MDR_SSP2,SSP_HCLKdiv16);
/* SSP1 MASTER configuration ------------------------------------------------*/
SSP_StructInit (&sSSP);
sSSP.SSP_SCR = 0x10;
sSSP.SSP_CPSDVSR = 2;
sSSP.SSP_Mode = SSP_ModeMaster;
sSSP.SSP_WordLength = SSP_WordLength16b;
sSSP.SSP_SPH = SSP_SPH_1Edge;
sSSP.SSP_SPO = SSP_SPO_Low;
sSSP.SSP_FRF = SSP_FRF_SPI_Motorola;
sSSP.SSP_HardwareFlowControl = SSP_HardwareFlowControl_SSE;
SSP_Init (MDR_SSP1,&sSSP);
/* SSP2 SLAVE configuration ------------------------------------------------*/
sSSP.SSP_SPH = SSP_SPH_1Edge;
sSSP.SSP_SPO = SSP_SPO_Low;
sSSP.SSP_CPSDVSR = 12;
sSSP.SSP_Mode = SSP_ModeSlave;
SSP_Init (MDR_SSP2,&sSSP);
/* Enable SSP1 DMA Rx and Tx request */
SSP_DMACmd(MDR_SSP1,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE);
/* Enable SSP2 DMA Rx and Tx request */
SSP_DMACmd(MDR_SSP2,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_SSP1_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP1->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf1;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_4;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP1_RX, &DMA_InitStr);
/* DMA_Channel_SSP2_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP2->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf2;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP2_RX, &DMA_InitStr);
/* DMA_Channel_SSP1_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf1;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP1->DR));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP1_TX, &DMA_InitStr);
/* DMA_Channel_SSP2_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf2;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP2->DR));
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP2_TX, &DMA_InitStr);
/* Enable SSP1 */
SSP_Cmd(MDR_SSP1, ENABLE);
/* Enable SSP2 */
SSP_Cmd(MDR_SSP2, ENABLE);
/* Transfer complete */
while((SSP_GetFlagStatus(MDR_SSP1, SSP_FLAG_BSY)))
{
}
while((SSP_GetFlagStatus(MDR_SSP2, SSP_FLAG_BSY)))
{
}
/* Check the corectness of written dada */
TransferStatus1 = Verif_mem ((BufferSize), SrcBuf1, DstBuf2);
TransferStatus2 = Verif_mem ((BufferSize), SrcBuf2, DstBuf1);
/* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
are correct */
/* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
are different */
while(1)
{
}
}
