/**
* @brief Low level NAND driver initialization.
*
* @notapi
*/
void nand_lld_init(void) {
fsmc_init();
#if STM32_NAND_USE_FSMC_NAND1
/* Driver initialization.*/
nandObjectInit(&NANDD1);
NANDD1.rxdata = NULL;
NANDD1.datalen = 0;
NANDD1.thread = NULL;
NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
NANDD1.nand = FSMCD1.nand1;
NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA;
NANDD1.map_cmd = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD;
NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR;
NANDD1.bb_map = NULL;
#endif /* STM32_NAND_USE_FSMC_NAND1 */
#if STM32_NAND_USE_FSMC_NAND2
/* Driver initialization.*/
nandObjectInit(&NANDD2);
NANDD2.rxdata = NULL;
NANDD2.datalen = 0;
NANDD2.thread = NULL;
NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
NANDD2.nand = FSMCD1.nand2;
NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA;
NANDD2.map_cmd = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD;
NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR;
NANDD2.bb_map = NULL;
#endif /* STM32_NAND_USE_FSMC_NAND2 */
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
ADC->CCR = STM32_ADC_ADCPRE;
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
#endif
#if STM32_ADC_USE_ADC2
/* Driver initialization.*/
adcObjectInit(&ADCD2);
ADCD2.adc = ADC2;
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
#endif
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
ADCD3.adc = ADC3;
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
}
/**
* @brief Low level UART driver initialization.
*
* @notapi
*/
void uart_lld_init(void) {
#if STM32_UART_USE_USART1
uartObjectInit(&UARTD1);
UARTD1.usart = USART1;
UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART2
uartObjectInit(&UARTD2);
UARTD2.usart = USART2;
UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART3
uartObjectInit(&UARTD3);
UARTD3.usart = USART3;
UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART6
uartObjectInit(&UARTD6);
UARTD6.usart = USART6;
UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
#endif
}
/**
* @brief Low level SDC driver initialization.
*
* @notapi
*/
void sdc_lld_init(void) {
sdcObjectInit(&SDCD1);
SDCD1.thread = NULL;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM);
SDCD1.sdio = SDIO;
}
/**
* @brief Low level SDC driver initialization.
*
* @notapi
*/
void sdc_lld_init(void) {
sdcObjectInit(&SDCD1);
SDCD1.thread = NULL;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC1_DMA_STREAM);
SDCD1.sdmmc = SDMMC1;
}
/**
* @brief Low level CRC driver initialization.
*
* @notapi
*/
void crc_lld_init(void) {
crcObjectInit(&CRCD1);
CRCD1.crc = CRC;
#if CRC_USE_DMA == TRUE
CRCD1.dma = STM32_DMA_STREAM(STM32_CRC_CRC1_DMA_STREAM);
#endif
}
void gpdrive_deinit(void) {
if (!m_init_done) {
return;
}
m_init_done = false;
timer_thd_stop = true;
while (timer_thd_stop) {
chThdSleepMilliseconds(1);
}
TIM_DeInit(TIM1);
TIM_DeInit(TIM12);
ADC_DeInit();
DMA_DeInit(DMA2_Stream4);
nvicDisableVector(ADC_IRQn);
dmaStreamRelease(STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 4)));
// Restore pins
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
}
*/
void sdc_lld_init(void) {
sdcObjectInit(&SDCD1);
SDCD1.thread = NULL;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM);
#if CH_DBG_ENABLE_ASSERTS
SDCD1.sdio = SDIO;
#endif
/**
* @brief Low level SDC driver initialization.
*
* @notapi
*/
void sdc_lld_init(void) {
#if STM32_SDC_USE_SDMMC1
sdcObjectInit(&SDCD1);
SDCD1.thread = NULL;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC1_DMA_STREAM);
SDCD1.sdmmc = SDMMC1;
nvicEnableVector(STM32_SDMMC1_NUMBER, STM32_SDC_SDMMC1_IRQ_PRIORITY);
#endif
#if STM32_SDC_USE_SDMMC2
sdcObjectInit(&SDCD2);
SDCD2.thread = NULL;
SDCD2.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC2_DMA_STREAM);
SDCD2.sdmmc = SDMMC2;
nvicEnableVector(STM32_SDMMC2_NUMBER, STM32_SDC_SDMMC2_IRQ_PRIORITY);
#endif
}
/**
* @brief Low level I2C driver initialization.
*
* @notapi
*/
void i2c_lld_init(void) {
#if STM32_I2C_USE_I2C1
i2cObjectInit(&I2CD1);
I2CD1.thread = NULL;
I2CD1.i2c = I2C1;
I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
#endif /* STM32_I2C_USE_I2C1 */
#if STM32_I2C_USE_I2C2
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
I2CD2.i2c = I2C2;
I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
#endif /* STM32_I2C_USE_I2C2 */
}
/**
* @brief Low level DAC driver initialization.
*
* @notapi
*/
void dac_lld_init(void) {
#if STM32_DAC_USE_CHN1
dacObjectInit(&DACD1);
DACD1.dac = DAC1;
DACD1.tim = STM32_TIM6;
DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY;
DACD1.dma = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM);
DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) | \
STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) | \
STM32_DMA_CR_DIR_M2P | \
STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_TEIE | \
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
#endif
#if STM32_DAC_USE_CHN2
dacObjectInit(&DACD2);
DACD2.dac = DAC1;
DACD2.tim = STM32_TIM7;
DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY;
DACD2.dma = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM);
DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) | \
STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \
STM32_DMA_CR_DIR_M2P | \
STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_TEIE | \
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
#endif
#if STM32_DAC_USE_CHN3
dacObjectInit(&DACD3);
DACD3.dac = DAC2;
DACD3.tim = STM32_TIM18;
DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY;
DACD3.dma = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM);
DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) | \
STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \
STM32_DMA_CR_DIR_M2P | \
STM32_DMA_CR_DMEIE | \
STM32_DMA_CR_TEIE | \
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
dummytx = 0xFFFF;
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
}
/**
* @brief Low level QSPI driver initialization.
*
* @notapi
*/
void qspi_lld_init(void) {
#if STM32_QSPI_USE_QUADSPI1
qspiObjectInit(&QSPID1);
QSPID1.qspi = QUADSPI;
QSPID1.dma = STM32_DMA_STREAM(STM32_QSPI_QUADSPI1_DMA_STREAM);
QSPID1.dmamode = STM32_DMA_CR_CHSEL(QUADSPI1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_QSPI_QUADSPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_BYTE |
STM32_DMA_CR_MSIZE_BYTE |
STM32_DMA_CR_MINC |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
nvicEnableVector(STM32_QUADSPI1_NUMBER, STM32_QSPI_QUADSPI1_IRQ_PRIORITY);
#endif
}
/**
* @brief Low level I2C driver initialization.
*
* @notapi
*/
void i2c_lld_init(void) {
#if STM32_I2C_USE_I2C1
i2cObjectInit(&I2CD1);
I2CD1.thread = NULL;
I2CD1.i2c = I2C1;
#if STM32_I2C_USE_DMA == TRUE
I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
#endif
#endif /* STM32_I2C_USE_I2C1 */
#if STM32_I2C_USE_I2C2
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
I2CD2.i2c = I2C2;
#if STM32_I2C_USE_DMA == TRUE
I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
#endif
#endif /* STM32_I2C_USE_I2C2 */
#if STM32_I2C_USE_I2C3
i2cObjectInit(&I2CD3);
I2CD3.thread = NULL;
I2CD3.i2c = I2C3;
#if STM32_I2C_USE_DMA == TRUE
I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM);
I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM);
#endif
#endif /* STM32_I2C_USE_I2C3 */
#if STM32_I2C_USE_I2C4
i2cObjectInit(&I2CD4);
I2CD4.thread = NULL;
I2CD4.i2c = I2C4;
#if STM32_I2C_USE_DMA == TRUE
I2CD4.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C4_RX_DMA_STREAM);
I2CD4.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C4_TX_DMA_STREAM);
#endif
#endif /* STM32_I2C_USE_I2C4 */
}
static void codec_dma_init(void)
{
i2sdma=STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
i2stxdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
bool_t b = dmaStreamAllocate(i2sdma,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)dma_i2s_interrupt,
(void *)&SPID3);
if (!b)
chprintf((BaseChannel*)&SD2, "DMA Allocated Successfully to I2S3\r\n");
dmaStreamSetPeripheral(i2sdma, &(SPI3->DR));
}
void usart_support_init(void)
{
SD1.usart = USART1;
SD1.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_TX_DMA_STREAM);
dmaStreamAllocate(SD1.tx.dma, STM32_SERIAL_USART1_PRIORITY,
(stm32_dmaisr_t)usart_tx_dma_isr, &SD1.tx);
SD1.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_RX_DMA_STREAM);
dmaStreamAllocate(SD1.rx.dma, STM32_SERIAL_USART1_PRIORITY,
(stm32_dmaisr_t)usart_rx_dma_isr, &SD1.rx);
SD1.dmamode = STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SERIAL_USART1_DMA_PRIORITY);
usart_support_init_tx(&SD1);
usart_support_init_rx(&SD1);
rccEnableUSART1(FALSE);
SD3.usart = USART3;
SD3.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_TX_DMA_STREAM);
dmaStreamAllocate(SD3.tx.dma, STM32_SERIAL_USART3_PRIORITY,
(stm32_dmaisr_t)usart_tx_dma_isr, &SD3.tx);
SD3.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_RX_DMA_STREAM);
dmaStreamAllocate(SD3.rx.dma, STM32_SERIAL_USART3_PRIORITY,
(stm32_dmaisr_t)usart_rx_dma_isr, &SD3.rx);
SD3.dmamode = STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SERIAL_USART3_DMA_PRIORITY);
usart_support_init_tx(&SD3);
usart_support_init_rx(&SD3);
rccEnableUSART3(FALSE);
SD6.usart = USART6;
SD6.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_TX_DMA_STREAM);
dmaStreamAllocate(SD6.tx.dma, STM32_SERIAL_USART6_PRIORITY,
(stm32_dmaisr_t)usart_tx_dma_isr, &SD6.tx);
SD6.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_RX_DMA_STREAM);
dmaStreamAllocate(SD6.rx.dma, STM32_SERIAL_USART6_PRIORITY,
(stm32_dmaisr_t)usart_rx_dma_isr, &SD6.rx);
SD6.dmamode = STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SERIAL_USART6_DMA_PRIORITY);
usart_support_init_tx(&SD6);
usart_support_init_rx(&SD6);
rccEnableUSART6(FALSE);
}
void gpdrive_init(volatile mc_configuration *configuration) {
utils_sys_lock_cnt();
m_init_done = false;
// Restore timers
TIM_DeInit(TIM1);
TIM1->CNT = 0;
// Disable channel 2 pins
palSetPadMode(GPIOA, 9, PAL_MODE_OUTPUT_PUSHPULL);
palClearPad(GPIOA, 9);
palSetPadMode(GPIOB, 14, PAL_MODE_OUTPUT_PUSHPULL);
palClearPad(GPIOB, 14);
m_conf = configuration;
m_fsw_now = 40000;
m_mod_now = 0.0;
m_current_now = 0.0;
m_current_now_filtered = 0.0;
m_output_mode = GPD_OUTPUT_MODE_NONE;
memset((void*)&m_sample_buffer, 0, sizeof(m_sample_buffer));
m_buffer_int_scale = 1.0 / 128.0;
m_is_running = false;
m_output_now = 0.0;
m_curr0_sum = 0;
m_curr1_sum = 0;
m_curr_samples = 0;
m_curr0_offset = 0;
m_curr1_offset = 0;
m_dccal_done = false;
#ifdef HW_HAS_3_SHUNTS
m_curr2_sum = 0;
m_curr2_offset = 0;
#endif
m_last_adc_isr_duration = 0;
memset((void*)&m_current_state, 0, sizeof(m_current_state));
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_Period = SYSTEM_CORE_CLOCK / (int)m_fsw_now;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OCInitStructure.TIM_Pulse = TIM1->ARR / 2;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Set;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
TIM_OC2Init(TIM1, &TIM_OCInitStructure);
TIM_OC3Init(TIM1, &TIM_OCInitStructure);
TIM_OC4Init(TIM1, &TIM_OCInitStructure);
TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
TIM_BDTRInitStructure.TIM_DeadTime = conf_general_calculate_deadtime(HW_DEAD_TIME_NSEC, SYSTEM_CORE_CLOCK);
TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
TIM_CCPreloadControl(TIM1, ENABLE);
TIM_ARRPreloadConfig(TIM1, ENABLE);
ADC_CommonInitTypeDef ADC_CommonInitStructure;
DMA_InitTypeDef DMA_InitStructure;
ADC_InitTypeDef ADC_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 | RCC_APB2Periph_ADC3, ENABLE);
dmaStreamAllocate(STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 4)),
3,
(stm32_dmaisr_t)adc_int_handler,
(void *)0);
DMA_InitStructure.DMA_Channel = DMA_Channel_0;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&ADC_Value;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&ADC->CDR;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_BufferSize = HW_ADC_CHANNELS;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(DMA2_Stream4, &DMA_InitStructure);
DMA_Cmd(DMA2_Stream4, ENABLE);
DMA_ITConfig(DMA2_Stream4, DMA_IT_TC, ENABLE);
// Note that the ADC is running at 42MHz, which is higher than the
// specified 36MHz in the data sheet, but it works.
ADC_CommonInitStructure.ADC_Mode = ADC_TripleMode_RegSimult;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_1;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
ADC_InitStructure.ADC_ScanConvMode = ENABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_Falling;
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC2;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = HW_ADC_NBR_CONV;
ADC_Init(ADC1, &ADC_InitStructure);
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
ADC_InitStructure.ADC_ExternalTrigConv = 0;
ADC_Init(ADC2, &ADC_InitStructure);
ADC_Init(ADC3, &ADC_InitStructure);
ADC_TempSensorVrefintCmd(ENABLE);
ADC_MultiModeDMARequestAfterLastTransferCmd(ENABLE);
hw_setup_adc_channels();
ADC_Cmd(ADC1, ENABLE);
ADC_Cmd(ADC2, ENABLE);
ADC_Cmd(ADC3, ENABLE);
TIM_Cmd(TIM1, ENABLE);
TIM_CtrlPWMOutputs(TIM1, ENABLE);
// Always sample ADC in the beginning of the PWM cycle
TIM1->CCR2 = 200;
utils_sys_unlock_cnt();
ENABLE_GATE();
DCCAL_OFF();
do_dc_cal();
// Start threads
timer_thd_stop = false;
chThdCreateStatic(timer_thread_wa, sizeof(timer_thread_wa), NORMALPRIO, timer_thread, NULL);
stop_pwm_hw();
// Check if the system has resumed from IWDG reset
if (timeout_had_IWDG_reset()) {
mc_interface_fault_stop(FAULT_CODE_BOOTING_FROM_WATCHDOG_RESET);
}
m_init_done = true;
}
/**
* @brief Low level UART driver initialization.
*
* @notapi
*/
void uart_lld_init(void) {
#if STM32_UART_USE_USART1
uartObjectInit(&UARTD1);
UARTD1.usart = USART1;
UARTD1.clock = STM32_USART1CLK;
UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART2
uartObjectInit(&UARTD2);
UARTD2.usart = USART2;
UARTD2.clock = STM32_USART2CLK;
UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART3
uartObjectInit(&UARTD3);
UARTD3.usart = USART3;
UARTD3.clock = STM32_USART3CLK;
UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_UART4
uartObjectInit(&UARTD4);
UARTD4.usart = UART4;
UARTD4.clock = STM32_UART4CLK;
UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_UART5
uartObjectInit(&UARTD5);
UARTD5.usart = UART5;
UARTD5.clock = STM32_UART5CLK;
UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART6
uartObjectInit(&UARTD6);
UARTD6.usart = USART6;
UARTD6.clock = STM32_USART6CLK;
UARTD6.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_UART7
uartObjectInit(&UARTD7);
UARTD7.usart = UART7;
UARTD7.clock = STM32_UART7CLK;
UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD7.dmarx = STM32_DMA_STREAM(STM32_UART_UART7_RX_DMA_STREAM);
UARTD7.dmatx = STM32_DMA_STREAM(STM32_UART_UART7_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_UART8
uartObjectInit(&UARTD8);
UARTD8.usart = UART8;
UARTD8.clock = STM32_UART8CLK;
UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD8.dmarx = STM32_DMA_STREAM(STM32_UART_UART8_RX_DMA_STREAM);
UARTD8.dmatx = STM32_DMA_STREAM(STM32_UART_UART8_TX_DMA_STREAM);
#endif
}
/**
* @brief Low level UART driver initialization.
*
* @notapi
*/
void uart_lld_init(void) {
#if STM32_UART_USE_USART1
uartObjectInit(&UARTD1);
UARTD1.usart = USART1;
UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART2
uartObjectInit(&UARTD2);
UARTD2.usart = USART2;
UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART3
uartObjectInit(&UARTD3);
UARTD3.usart = USART3;
UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_UART4
uartObjectInit(&UARTD4);
UARTD4.usart = UART4;
UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD4.dmarx = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
UARTD4.dmatx = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_UART5
uartObjectInit(&UARTD5);
UARTD5.usart = UART5;
UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD5.dmarx = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
UARTD5.dmatx = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
#endif
#if STM32_UART_USE_USART6
uartObjectInit(&UARTD6);
UARTD6.usart = USART6;
UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
#endif
}
/**
* @brief Low level I2S driver initialization.
*
* @notapi
*/
void i2s_lld_init(void) {
#if STM32_I2S_USE_SPI2
i2sObjectInit(&I2SD2);
I2SD2.spi = SPI2;
I2SD2.cfg = STM32_I2S2_CFGR_CFG;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmarx = NULL;
I2SD2.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD2.dmatx = NULL;
I2SD2.txdmamode = 0;
#endif
#endif
#if STM32_I2S_USE_SPI3
i2sObjectInit(&I2SD3);
I2SD3.spi = SPI3;
I2SD3.cfg = STM32_I2S3_CFGR_CFG;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmarx = NULL;
I2SD3.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmatx = NULL;
I2SD3.txdmamode = 0;
#endif
#endif
}
/** @brief DAC2 CH2 driver identifier.*/
#if (STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
DACDriver DACD4;
#endif
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
#if STM32_DAC_USE_DAC1_CH1 == TRUE
static const dacparams_t dma1_ch1_params = {
.dac = DAC1,
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC1_CH1_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC1_CH2 == TRUE
static const dacparams_t dma1_ch2_params = {
.dac = DAC1,
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI4
spiObjectInit(&SPID4);
SPID4.spi = SPI4;
SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI5
spiObjectInit(&SPID5);
SPID5.spi = SPI5;
SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI6
spiObjectInit(&SPID6);
SPID6.spi = SPI6;
SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
clkmask = 0;
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
#if defined(ADC1_2_COMMON)
ADCD1.adcc = ADC1_2_COMMON;
#elif defined(ADC123_COMMON)
ADCD1.adcc = ADC123_COMMON;
#else
ADCD1.adcc = ADC1_COMMON;
#endif
ADCD1.adcm = ADC1;
#if STM32_ADC_DUAL_MODE
ADCD1.adcs = ADC2;
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD1.dmastp = NULL;
#else
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
#endif
ADCD1.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC1 */
#if STM32_ADC_USE_ADC2
/* Driver initialization.*/
adcObjectInit(&ADCD2);
#if defined(ADC1_2_COMMON)
ADCD2.adcc = ADC1_2_COMMON;
#elif defined(ADC123_COMMON)
ADCD2.adcc = ADC123_COMMON;
#endif
ADCD2.adcm = ADC2;
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD2.dmastp = NULL;
#else
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
#endif
ADCD2.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC2 */
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
#if defined(ADC3_4_COMMON)
ADCD3.adcc = ADC3_4_COMMON;
#elif defined(ADC123_COMMON)
ADCD3.adcc = ADC123_COMMON;
#else
ADCD3.adcc = ADC3_COMMON;
#endif
ADCD3.adcm = ADC3;
#if STM32_ADC_DUAL_MODE
ADCD3.adcs = ADC4;
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD3.dmastp = NULL;
#else
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
#endif
ADCD3.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC3 */
#if STM32_ADC_USE_ADC4
/* Driver initialization.*/
adcObjectInit(&ADCD4);
ADCD4.adcc = ADC3_4_COMMON;
ADCD4.adcm = ADC4;
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD4.dmastp = NULL;
#else
ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
#endif
ADCD4.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC4 */
/* IRQs setup.*/
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);
#endif
#if STM32_ADC_USE_ADC3
nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
#if STM32_ADC_DUAL_MODE
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
#endif
#endif
#if STM32_ADC_USE_ADC4
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
#endif
/* ADC units pre-initializations.*/
#if defined(STM32F3XX)
#if STM32_HAS_ADC1 && STM32_HAS_ADC2
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
rccEnableADC12(true);
rccResetADC12();
ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12();
#endif
#else
#if STM32_ADC_USE_ADC1
rccEnableADC12(true);
rccResetADC12();
ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12();
#endif
#endif
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
rccEnableADC34(true);
rccResetADC34();
ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC34();
#endif
#endif
#if defined(STM32L4XX) || defined(STM32L4XXP)
rccEnableADC123(true);
rccResetADC123();
#if defined(ADC1_2_COMMON)
ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
#elif defined(ADC123_COMMON)
ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
#else
ADC1_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
#endif
rccDisableADC123();
#endif
}
#include "ch.h" // needs for all ChibiOS programs #include "hal.h" // hardware abstraction layer header #include "vex.h" // vex library header // number of samples we use for the basic sine wave that all sounds are // created from // If this changes then change the pre-calculated sin values #define WAVE_SAMPLES 32 // global storage for sine wave static uint16_t Sine12bit[WAVE_SAMPLES]; // dma STREAM FOR dac static const stm32_dma_stream_t *vsl_dma = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 3)); // counter for sound output timer static volatile uint32_t VSL_Counter = 0; // the audio task static Thread *vslThread = NULL; // event source to indicate sound is finished. static EVENTSOURCE_DECL(sound_done); // semaphore used to wake audio thread static Semaphore vslSem; // working area for background thread #define AUDIO_WA_SIZE THD_WA_SIZE(AUDIO_TASK_STACK_SIZE)
