void stm32f_fsmc_init(void)
{
struct stm32f_fsmc * fsmc = STM32F_FSMC;
DCC_LOG(LOG_TRACE, ".");
/* Flexible static memory controller module clock enable */
stm32_clk_enable(STM32_RCC, STM32_CLK_FSMC);
#if 0
int i;
/* Configure IO pins */
stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD);
stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE);
for (i = 0; i < sizeof(fsmc_io) / sizeof(gpio_io_t); i++) {
gpio_io_t io = fsmc_io[i];
stm32_gpio_mode(STM32_GPIO(io.port), io.pin,
ALT_FUNC, PUSH_PULL | SPEED_HIGH);
stm32_gpio_af(STM32_GPIO(io.port), io.pin, GPIO_AF12);
}
stm32_gpio_mode(STM32_GPIO(GPIOD), 6, INPUT, PUSH_PULL | SPEED_HIGH);
#endif
fsmc->bcr1 = FSMC_CBURSTRW |
FSMC_WREN |
FSMC_BURSTEN |
FSMC_MWID_16 |
FSMC_MTYP_PSRAM |
FSMC_MUXEN | /* Address/Data multiplexed */
FSMC_MBKEN |
FSMC_WAITEN |
FSMC_WAITPOL;
fsmc->btr1 = FSMC_ACCMOD_A | FSMC_DATLAT_SET(0) |
FSMC_CLKDIV_SET(3) | FSMC_BUSTURN_SET(0) |
FSMC_DATAST_SET(0) | FSMC_ADDHDL_SET(0) |
FSMC_ADDSET_SET(0);
fsmc->bwtr1 = FSMC_ACCMOD_A | FSMC_DATLAT_SET(0) |
FSMC_CLKDIV_SET(1) | FSMC_BUSTURN_SET(0) |
FSMC_DATAST_SET(0) | FSMC_ADDHDL_SET(0) |
FSMC_ADDSET_SET(0);
}
int lis302_init(void)
{
struct stm32f_spi * spi = STM32F_SPI1;
gpio_io_t io;
io = lis302_cs ;
stm32_gpio_clock_en(STM32_GPIO(io.port));
stm32_gpio_mode(STM32_GPIO(io.port), io.pin, OUTPUT, SPEED_MED);
gpio_set(io);
stm32f_spi_init(spi, &spi1_io, 500000, SPI_MSTR | SPI_CPOL | SPI_CPHA);
spi->cr2 = SPI_TXEIE | SPI_RXNEIE;
return 0;
}
struct file * stm32_usart_open(struct stm32_usart * us,
unsigned int baudrate, unsigned int flags)
{
int id;
if ((id = stm32_usart_init(us)) < 0) {
return NULL;
}
io_rxd_cfg(STM32_GPIO(cfg[id].rx.port), cfg[id].rx.pin, cfg[id].af);
io_txd_cfg(STM32_GPIO(cfg[id].tx.port), cfg[id].tx.pin, cfg[id].af);
stm32_usart_baudrate_set(us, baudrate);
stm32_usart_mode_set(us, flags);
stm32_usart_enable(us);
return (struct file *)&stm32f_uart_file[id];
}
int stm32f_spi_init(struct stm32f_spi * spi,
const struct stm32f_spi_io * spi_io,
unsigned int freq, unsigned int opt)
{
struct stm32_rcc * rcc = STM32_RCC;
gpio_io_t io;
uint32_t div;
int br;
int id;
if ((id = stm32f_spi_lookup(spi)) < 0) {
/* invalid SPI ??? */
return id;
}
/* Configure IO pins */
io = spi_io->miso;
stm32_gpio_clock_en(STM32_GPIO(io.port));
stm32_gpio_mode(STM32_GPIO(io.port), io.pin, ALT_FUNC,
PULL_UP | SPEED_MED);
stm32_gpio_af(STM32_GPIO(io.port), io.pin, spi_cfg[id].af);
io = spi_io->mosi;
stm32_gpio_clock_en(STM32_GPIO(io.port));
stm32_gpio_mode(STM32_GPIO(io.port), io.pin, ALT_FUNC,
PUSH_PULL | SPEED_MED);
stm32_gpio_af(STM32_GPIO(io.port), io.pin, spi_cfg[id].af);
io = spi_io->sck;
stm32_gpio_clock_en(STM32_GPIO(io.port));
stm32_gpio_mode(STM32_GPIO(io.port), io.pin, ALT_FUNC,
PUSH_PULL | SPEED_MED);
stm32_gpio_af(STM32_GPIO(io.port), io.pin, spi_cfg[id].af);
/* Enable peripheral clock */
if (spi_cfg[id].apb2) {
rcc->apb2enr |= (1 << spi_cfg[id].ckbit);
div = stm32f_apb2_hz / freq / 2;
} else {
rcc->apb1enr |= (1 << spi_cfg[id].ckbit);
div = stm32f_apb1_hz / freq / 2;
}
br = 31 - __clz(div);
if (div > (1 << br)) {
br++;
}
DCC_LOG3(LOG_TRACE, "SPI id=%d div=%d br=%d", id, div, br);
spi->cr1 = 0;
spi->cr2 = 0;
spi->i2scfgr = 0;
spi->i2spr = 0;
spi->cr1 = SPI_SPE | SPI_BR_SET(br) | opt | SPI_SSM | SPI_SSI;
#if 0
spi->cr1 = SPI_SPE | SPI_MSTR | SPI_SSM | SPI_SSI | \
SPI_BR_SET(br) | SPI_LSBFIRST;
#endif
return id;
}
