uint16_t send_packet() {
seqnum++;
hello.seqnum[0] = seqnum ;
hello.seqnum[1] = seqnum >> 8;
/* Add data in the hello message here */
hello.crc = crc8_bytes((uint8_t *)hello.raw, (uint16_t)ST_OFFSET(hello_t, crc) );
mac_send(MAC_BROADCAST_ADDR, hello.raw, sizeof(hello_t), 0);
return 0;
}
static CORE_ADDR
m88k_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR pc, CORE_ADDR limit,
struct m88k_frame_cache *cache)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR end = limit;
/* Provide a dummy cache if necessary. */
if (cache == NULL)
{
size_t sizeof_saved_regs =
(M88K_R31_REGNUM + 1) * sizeof (struct trad_frame_saved_reg);
cache = alloca (sizeof (struct m88k_frame_cache));
cache->saved_regs = alloca (sizeof_saved_regs);
/* We only initialize the members we care about. */
cache->saved_regs[M88K_R1_REGNUM].addr = -1;
cache->fp_offset = -1;
}
while (pc < limit)
{
struct m88k_prologue_insn *pi = m88k_prologue_insn_table;
unsigned long insn = m88k_fetch_instruction (pc, byte_order);
while ((insn & pi->mask) != pi->insn)
pi++;
switch (pi->action)
{
case M88K_PIA_SKIP:
/* If we have a frame pointer, and R1 has been saved,
consider this instruction as not being part of the
prologue. */
if (cache->fp_offset != -1
&& cache->saved_regs[M88K_R1_REGNUM].addr != -1)
return min (pc, end);
break;
case M88K_PIA_NOTE_ST:
case M88K_PIA_NOTE_STD:
/* If no frame has been allocated, the stores aren't part of
the prologue. */
if (cache->sp_offset == 0)
return min (pc, end);
/* Record location of saved registers. */
{
int regnum = ST_SRC (insn) + M88K_R0_REGNUM;
ULONGEST offset = ST_OFFSET (insn);
cache->saved_regs[regnum].addr = offset;
if (pi->action == M88K_PIA_NOTE_STD && regnum < M88K_R31_REGNUM)
cache->saved_regs[regnum + 1].addr = offset + 4;
}
break;
case M88K_PIA_NOTE_SP_ADJUSTMENT:
/* A second stack pointer adjustment isn't part of the
prologue. */
if (cache->sp_offset != 0)
return min (pc, end);
/* Store stack pointer adjustment. */
cache->sp_offset = -SUBU_OFFSET (insn);
break;
case M88K_PIA_NOTE_FP_ASSIGNMENT:
/* A second frame pointer assignment isn't part of the
prologue. */
if (cache->fp_offset != -1)
return min (pc, end);
/* Record frame pointer assignment. */
cache->fp_offset = ADDU_OFFSET (insn);
break;
case M88K_PIA_NOTE_BRANCH:
/* The branch instruction isn't part of the prologue, but
the instruction in the delay slot might be. Limit the
prologue analysis to the delay slot and record the branch
instruction as the end of the prologue. */
limit = min (limit, pc + 2 * M88K_INSN_SIZE);
end = pc;
break;
case M88K_PIA_NOTE_PROLOGUE_END:
return min (pc, end);
}
pc += M88K_INSN_SIZE;
}
return end;
}
