/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
/* Init System, IP clock and multi-function I/O
In the end of SYS_Init() will issue SYS_LockReg()
to lock protected register. If user want to write
protected register, please issue SYS_UnlockReg()
to unlock protected register if necessary */
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART to 115200-8n1 for print message */
UART0_Init();
printf("\n\nCPU @ %dHz(PLL@ %dHz)\n", SystemCoreClock, PllClock);
printf("PWM0 clock is from %s\n", (CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk) ? "CPU" : "PLL");
printf("+------------------------------------------------------------------------+\n");
printf("| PWM Driver Sample Code |\n");
printf("| |\n");
printf("+------------------------------------------------------------------------+\n");
printf(" This sample code will output PWM0 channel 0~3 with different\n");
printf(" frequency and duty, enable dead zone function of all PWM0 pairs.\n");
printf(" And also enable/disable PWM output every 1 second.\n");
printf(" I/O configuration:\n");
printf(" waveform output pin: PWM0_CH0(PC.0), PWM0_CH1(PC.1), PWM0_CH2(PC.2), PWM0_CH3(PC.3)\n");
/*Set Pwm mode as complementary mode*/
PWM_ENABLE_COMPLEMENTARY_MODE(PWM0);
// PWM0 channel 0 frequency is 100Hz, duty 30%,
PWM_ConfigOutputChannel(PWM0, 0, 100, 30);
SYS_UnlockReg();
PWM_EnableDeadZone(PWM0, 0, 400);
SYS_LockReg();
// PWM0 channel 2 frequency is 300Hz, duty 50%
PWM_ConfigOutputChannel(PWM0, 2, 300, 50);
SYS_UnlockReg();
PWM_EnableDeadZone(PWM0, 2, 200);
SYS_LockReg();
// Enable output of PWM0 channel 0~3
PWM_EnableOutput(PWM0, 0xF);
// Enable PWM0 channel 0 period interrupt, use channel 0 to measure time.
PWM_EnablePeriodInt(PWM0, 0, 0);
NVIC_EnableIRQ(PWM0P0_IRQn);
// Start
PWM_Start(PWM0, 0xF);
while(1);
}
void close_pwm(char channel)
{
/*--------------------------------------------------------------------------------------*/
/* Stop PWM Timer (Recommended procedure method 2) */
/* Set PWM Timer counter as 0, When interrupt request happen, disable PWM Timer */
/* Set PWM Timer counter as 0 in Call back function */
/*--------------------------------------------------------------------------------------*/
char pwm_channel;
if(channel==1)
{
pwm_channel=PWM_CH1;
PWMA->PIER &= ~PWM_PIER_PWMIE1_Msk;
}
else
{
pwm_channel=PWM_CH0;
PWMA->PIER &= ~PWM_PIER_PWMIE0_Msk;
}
/* Disable PWMB NVIC */
//NVIC_DisableIRQ((IRQn_Type)(PWMA_IRQn));
/* Wait until PWMB channel 0 Timer Stop */
if(channel==1)
{
while(PWMA->PDR1!=0);
linght_gray1=0;
}
else
{
while(PWMA->PDR0!=0);
linght_gray0=0;
}
/* Disable the PWM Timer */
_PWM_DISABLE_TIMER(PWMA,pwm_channel);
/* Disable PWM Output pin */
_PWM_DISABLE_PWM_OUT(PWMA, pwm_channel);
if(channel==1)
{
SYS_UnlockReg();
SYS->P2_MFP |= SYS_MFP_P21_GPIO;
SYS_LockReg();
_GPIO_SET_PIN_MODE(P2,1,GPIO_PMD_OUTPUT);
P21=0;
}
else
{
SYS_UnlockReg();
SYS->P2_MFP |= SYS_MFP_P20_GPIO;
SYS_LockReg();
_GPIO_SET_PIN_MODE(P2,0,GPIO_PMD_OUTPUT);
P20=0;
}
}
/*---------------------------------------------------------------------------------------------------------*/
int main(void)
{
uint32_t u32IntCnts = 0;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("CPU @ %d Hz\n", SystemCoreClock);
printf("+------------------------------------------+\n");
printf("| WDT Time-out Interrupt Sample Code |\n");
printf("+------------------------------------------+\n\n");
printf("# WDT Settings:\n");
printf(" - Clock source is 10 kHz \n");
printf(" - Time-out interval is 2^14 * WDT clock \n");
printf(" (around 1.6384 second) \n");
printf(" - Interrupt enable \n");
printf("# System will generate a WDT time-out interrupt event after around 1.6384 second.\n");
printf(" (Use PA.0 high/low period time to check WDT time-out interval)\n\n");
/* Use PA.0 to check time-out period time */
GPIO_SetMode(PA, BIT0, GPIO_PMD_OUTPUT);
PA0 = 1;
PA0 = 0;
/* Because of all bits can be written in WDT Control Register are write-protected;
To program it needs to disable register protection first. */
SYS_UnlockReg();
/* Select WDT time-out interval to 2^14 * WDT clock then start WDT counting */
g_u8IsWDTTimeoutINT = 0;
WDT_Open(WDT_TIMEOUT_2POW14, 0, FALSE, FALSE);
/* Enable WDT interrupt function */
WDT_EnableInt();
/* Enable WDT NVIC */
NVIC_EnableIRQ(WDT_IRQn);
while(1)
{
/* Check if WDT time-out interrupt occurred or not */
while(g_u8IsWDTTimeoutINT == 0);
g_u8IsWDTTimeoutINT = 0;
PA0 ^= 1;
printf("WDT time-out interrupt occurred. INT counts: %d \r", ++u32IntCnts);
}
}
/*---------------------------------------------------------------------------------------------------------*/
int main(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
if(WDT_GET_RESET_FLAG() == 1) {
/* Use PA.0 to check time-out period time */
GPIO_SetMode(PA, BIT0, GPIO_PMD_OUTPUT);
PA0 = 1;
WDT_CLEAR_RESET_FLAG();
printf("\n\n*** WDT time-out reset occurred ***\n");
while(1);
}
printf("\n\nCPU @ %d Hz\n", SystemCoreClock);
printf("+--------------------------------------+\n");
printf("| WDT Time-out Reset Sample Code |\n");
printf("+--------------------------------------+\n\n");
printf("# WDT Settings:\n");
printf(" Clock source is 10 kHz; Enable interrupt; Time-out interval is 2^14 * WDT clock.\n");
printf("# When WDT start counting, system will generate a WDT time-out interrupt after 1.6384 ~ 1.7408 s.\n");
printf(" Measure PA.0 low period to check time-out interval and do not reload WDT counter will cause system reset.\n\n");
/* Use PA.0 to check time-out period time */
GPIO_SetMode(PA, BIT0, GPIO_PMD_OUTPUT);
PA0 = 1;
PA0 = 0;
/* Because of all bits can be written in WDT Control Register are write-protected;
To program it needs to disable register protection first. */
SYS_UnlockReg();
/* Enable WDT time-out reset function and select time-out interval to 2^14 * WDT clock then start WDT counting */
g_u8IsWDTTimeoutINT = 0;
WDT_Open(WDT_TIMEOUT_2POW14, WDT_RESET_DELAY_1026CLK, TRUE, FALSE);
/* Enable WDT interrupt function */
WDT_EnableInt();
/* Enable WDT NVIC */
NVIC_EnableIRQ(WDT_IRQn);
while(1);
}
__myevic__ void Plantouille( int xpsr, int* stack )
{
int i, k;
k = 0;
SYS_UnlockReg();
WDT_Close();
SYS_LockReg();
InitDisplay();
while ( 1 )
{
ClearScreenBuffer();
DrawImage( 0, 0, 'X'+0x27 );
DrawHexLong( 16, 0, xpsr, 0 );
DrawHexDigit( 0, 16, k );
for ( i = 0; i < 14 ; ++i )
{
DrawHexLong( 16, 16+i*8, stack[i+k*14], 0 );
}
DisplayRefresh();
while ( !PE0 || !PD2 || !PD3 )
CLK_SysTickDelay( 10000 );
while ( PE0 && PD2 && PD3 )
CLK_SysTickDelay( 10000 );
if ( !PE0 )
{
SYS_UnlockReg();
SYS_ResetChip();
while ( 1 )
;
}
if ( !PD2 ) ++k;
if ( !PD3 ) --k;
if ( k < 0 ) k = 0;
else if ( k > 15 ) k = 15;
}
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));
/* Set HCLK frequency 42MHz */
CLK_SetCoreClock(42000000);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */
SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);
SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);
/* Lock protected registers */
SYS_LockReg();
}
void SPIClass::begin() {
if(init_flag==0); //init();
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable IP clock */
CLK_EnableModuleClock(SPI1_MODULE);
/* Select IP clock source and clock divider */
CLK_SetModuleClock(SPI1_MODULE,CLK_CLKSEL1_SPI1_S_HCLK,MODULE_NoMsk);
SYS->GPC_MFP |= SYS_GPC_MFP_PC11_SPI1_MOSI0;
SYS->GPA_MFP |= SYS_GPA_MFPH_GPA10_MFP_SPI1_MISO0 | SYS_GPA_MFPH_GPA11_MFP_SPI1_CLK;
SYS->ALT_MFP |= SYS_ALT_MFP_PC11_SPI1_MOSI0 | SYS_ALT_MFP_PA11_SPI1_CLK | SYS_ALT_MFP_PA10_SPI1_MISO0;
/* Lock protected registers */
SYS_LockReg();
/* Configure as a master, clock idle low, falling clock edge Tx, rising edge Rx and 8-bit transaction */
/* Set IP clock divider. SPI clock rate = 12MHz */
SPI_Open(spi, SPI_MASTER, SPI_MODE_0, 8, 6000000);
//SPI_EnableFIFO(spi,2,2); //ouki
setBitOrder(SS, MSBFIRST);
}
void setupSystemClock()
{
SYS_UnlockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable external XTAL 12MHz clock */
//CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for external XTAL clock ready */
//CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(SYSTEM_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External XTAL (4~24 MHz) */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for 12MHz clock ready */
SYS_WaitingForClockReady( SYSCLK_CLKSTATUS_XTL12M_STB_Msk);
/* Switch HCLK clock source to XTAL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_XTAL;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_ADC_EN_Msk ;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_XTAL | SYSCLK_CLKSEL1_ADC_XTAL ;
/* Set ADC divisor */
_ADC_SET_CLK_DIV(7);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB1_TXD0 | SYS_GPB_MFP_PB0_RXD0;
/* Disable the GPA0 - GPA3 digital input path to avoid the leakage current. */
PA->OFFD = (GPIO_OFFD_ENABLE(0)|GPIO_OFFD_ENABLE(1)|GPIO_OFFD_ENABLE(2)|GPIO_OFFD_ENABLE(3));
/* Configure the GPA0 - GPA3 ADC analog input pins */
SYS->GPA_MFP = SYS_GPA_MFP_PA0_ADC0 | SYS_GPA_MFP_PA1_ADC1 | SYS_GPA_MFP_PA2_ADC2 | SYS_GPA_MFP_PA3_ADC3 ;
SYS->ALT_MFP1 = 0;
/* Lock protected registers */
SYS_LockReg();
}
void UpdateBoardVersion(bool erase)
{
/* Enable ISP function */
#ifdef M451
SYS_UnlockReg();
FMC_Open();
#else
DrvFMC_EnableISP();
#endif
if(erase) {
DATA_FLASH_Write(BOARD_CODE_BASE,0xffffffff);
}
else {
BoardVersion = DATA_FLASH_Read(BOARD_CODE_BASE);
if(BoardVersion==0xFFFFFFFF) {
DATA_FLASH_Write(BOARD_CODE_BASE,BOARD_CODE);
printf("Update Board Code:%d\n", BOARD_CODE);
}
else
printf("Board Code:%d\n", BoardVersion);
}
#ifdef M451
FMC_Close();
SYS_LockReg();
#else
DrvFMC_DisableISP();
#endif
}
void write_impl(uint8_t * addressE, const uint8_t * data, int size)
{
SYS_UnlockReg();
/* Enable FMC ISP function */
FMC_Open();
while(size > 0) {
int adr = (int) addressE & (PAGE_SIZE - 1);
int less_size;
if(adr+size > PAGE_SIZE) {
less_size = PAGE_SIZE - adr;
} else {
less_size = size;
}
write_impl_less(addressE, data, less_size);
addressE += less_size;
data += less_size;
size -= less_size;
}
/* Disable FMC ISP function */
FMC_Close();
SYS_LockReg();
}
void open_pwm3(void)
{
SYS_UnlockReg();
SYS->P2_MFP |= SYS_MFP_P23_PWM3;
SYS_LockReg();
/*Set Pwm mode*/
_PWM_SET_TIMER_AUTO_RELOAD_MODE(PWMA,PWM_CH3);
/*Set PWM Timer clock prescaler*/
_PWM_SET_TIMER_PRESCALE(PWMA,PWM_CH3,2); // Divided by 2
/*Set PWM Timer clock divider select*/
_PWM_SET_TIMER_CLOCK_DIV(PWMA,PWM_CH3,PWM_CSR_DIV16);
PWMA->CMR3 = Brightness[19];
/*Set PWM Timer period*/
PWMA->CNR3 = 0xffff;
/* Enable PWM Output pin */
_PWM_ENABLE_PWM_OUT(PWMA,PWM_CH3);
/* Enable Timer period Interrupt */
_PWM_ENABLE_TIMER_PERIOD_INT(PWMA,PWM_CH3);
/* Enable PWMB NVIC */
NVIC_EnableIRQ((IRQn_Type)(PWMA_IRQn));
/* Enable PWM Timer */
_PWM_ENABLE_TIMER(PWMA,PWM_CH3);
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
SYSCLK->PWRCON |= SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for IRC22M clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Enable external 12MHz XTAL, internal 22.1184MHz */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk | SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Enable PLL and Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk | SYSCLK_CLKSTATUS_XTL12M_STB_Msk | SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_STCLK_HCLK_DIV2 | SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_PWM01_EN_Msk | SYSCLK_APBCLK_PWM23_EN_Msk | SYSCLK_APBCLK_TMR0_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_PWM01_XTAL | SYSCLK_CLKSEL1_PWM23_XTAL |SYSCLK_CLKSEL1_TMR0_XTAL;
/* Reset PWMB channel0~channel3 and Reset TIMER0*/
SYS->IPRSTC2 = SYS_IPRSTC2_PWM03_RST_Msk | SYS_IPRSTC2_TMR0_RST_Msk;
SYS->IPRSTC2 = 0;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P2 multi-function pins for PWMA Channel0~3 */
//SYS->P2_MFP = SYS_MFP_P20_PWM0|SYS_MFP_P21_PWM1|SYS_MFP_P22_PWM2;
SYS->P2_MFP = SYS_MFP_P22_PWM2;
/* Lock protected registers */
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
printf("+---------------------------------------+\n");
printf("| MINI58 System Driver Sample Code |\n");
printf("+---------------------------------------+\n");
/* Unlock protected registers for Brown-Out Detector settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if(SYS_IsRegLocked() == 0)
{
printf("Protected Address is Unlocked\n");
}
/* Run PLL Test */
SYS_PLL_Demo();
printf("Exit\n");
while(1);
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable external 12MHz XTAL, internal 22.1184MHz */
CLK->PWRCON |= CLK_PWRCON_XTL12M | CLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL_STB_Msk | CLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to XTL, STCLK to XTL */
CLK->CLKSEL0 = CLK_CLKSEL0_STCLK_S_XTAL | CLK_CLKSEL0_HCLK_S_XTAL;
/* Enable IP clock */
CLK->APBCLK = CLK_APBCLK_UART_EN_Msk;
/* Select IP clock source */
CLK->CLKSEL1 = CLK_CLKSEL1_UART_S_XTAL;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P0 multi-function pins for UART RXD and TXD */
SYS->P0_MFP = SYS_MFP_P01_RXD | SYS_MFP_P00_TXD;
/* Lock protected registers */
SYS_LockReg();
/* Update System Core Clock */
SystemCoreClockUpdate();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External XTAL (4~24 MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for 12MHz clock ready */
CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);
/* Switch HCLK clock source to HXT */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
/* Set PLL frequency */
CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Switch HCLK clock source to PLL */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
CLK_EnableModuleClock(SPI0_MODULE);
CLK_EnableModuleClock(SPI1_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPG multi-function pins for UART0 RXD and TXD */
SYS->GPG_MFPL = SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD ;
/* SPI0: GPE4=SS0, GPE3=MOSI0, GPE2=MISO0, GPE5=CLK */
SYS->GPE_MFPL = (SYS_GPE_MFPL_PE2MFP_SPI0_MISO0 | SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0 | SYS_GPE_MFPL_PE4MFP_SPI0_SS0 | SYS_GPE_MFPL_PE5MFP_SPI0_CLK);
/* SPI1: GPC12=SS0, GPC15=MOSI0, GPD0=MISO0, GPD1=CLK */
SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_SPI1_SS0 | SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0);
SYS->GPD_MFPL = (SYS_GPD_MFPL_PD0MFP_SPI1_MISO0 | SYS_GPD_MFPL_PD1MFP_SPI1_CLK);
/* Lock protected registers */
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
int main(void)
{
volatile uint32_t u32InitCount;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
init_neuron_system();
init_block();
while(1)
{
// protocol.
parse_uart0_recv_buffer();
flush_uart1_to_uart0();
flush_uart0_local_buffer();
// led
poll_led_request();
}
}
void GoToSleep()
{
gFlags.light_sleep = !( gFlags.has_x32 || dfStatus.lsloff || gFlags.noclock );
ScreenOff();
LEDOff();
gFlags.firing = 0;
BatReadTimer = 50;
RTCSleep();
DevicesOnOff( 1 );
CLK_SysTickDelay( 250 );
CLK_SysTickDelay( 250 );
CLK_SysTickDelay( 250 );
if ( dfStatus.off || PE0 || KeyPressTime == 1100 )
{
SYS_UnlockReg();
WDT_Close();
FlushAndSleep();
PreheatDelay = 0;
}
WDT_Open( WDT_TIMEOUT_2POW14, WDT_RESET_DELAY_18CLK, TRUE, FALSE );
SYS_LockReg();
gFlags.refresh_battery = 1;
DevicesOnOff( 0 );
RTCWakeUp();
InitDisplay();
}
int main(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf and testing */
UART0_Init();
/*---------------------------------------------------------------------------------------------------------*/
/* SAMPLE CODE */
/*---------------------------------------------------------------------------------------------------------*/
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
printf("\n\nUART Sample Program\n");
/* UART sample function */
UART_FunctionTest();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
SYSCLK->PWRCON |= SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for IRC22M clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to internal RC */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Enable external 12MHz XTAL, 10kHz */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk | SYSCLK_PWRCON_IRC10K_EN_Msk;
/* Enable PLL and Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk | SYSCLK_CLKSTATUS_XTL12M_STB_Msk | SYSCLK_CLKSTATUS_IRC10K_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_STCLK_HCLK_DIV2 | SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->AHBCLK = SYSCLK_AHBCLK_ISP_EN_Msk;
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_SPI0_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_PLL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
/* Set P1.4, P1.5, P1.6, P1.7 for SPI0 */
SYS->P1_MFP = SYS_MFP_P14_SPISS0 | SYS_MFP_P15_MOSI_0 | SYS_MFP_P16_MISO_0 | SYS_MFP_P17_SPICLK0;
/* Lock protected registers */
SYS_LockReg();
}
int main() {
int i;
// The virtual COM port is not initialized by default.
// To initialize it, follow those steps:
// 1) Unlock system control registers.
SYS_UnlockReg();
// 2) Initialize the virtual COM port.
USB_VirtualCOM_Init();
// 3) Lock system control registers.
SYS_LockReg();
// Display some text, just to know it's working
Display_PutText(0, 0, "USB OK.", FONT_DEJAVU_8PT);
Display_Update();
while(1) {
// Send string over the virtual COM port
USB_VirtualCOM_SendString("Hello, USB!\r\n");
// Wait 3 seconds
for(i=0;i<30;i++) {
Timer_DelayUs(100000);
}
}
}
/*---------------------------------------------------------------------------------------------------------*/
int main(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %d Hz\n", SystemCoreClock);
printf("+-------------------------------------------------------+\n");
printf("| GPIO Power-Down and Wake-up by PB.3 Sample Code |\n");
printf("+-------------------------------------------------------+\n\n");
/* Configure PB.3 as Input mode and enable interrupt by rising edge trigger */
GPIO_SetMode(PB, BIT3, GPIO_PMD_INPUT);
GPIO_EnableInt(PB, 3, GPIO_INT_RISING);
NVIC_EnableIRQ(GPAB_IRQn);
/* Waiting for PB.3 rising-edge interrupt event */
while(1) {
printf("Enter to Power-Down ......\n");
PowerDownFunction();
UART_WAIT_TX_EMPTY(UART0);
printf("System waken-up done.\n\n");
}
}
/*--------------------------------------------------------------------------*/
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable external 12MHz HXT */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, 96000000);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_PLL_STB_Msk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(3));
/* Select IP clock source */
CLK_SetModuleClock(USBD_MODULE, 0, CLK_USB_CLK_DIVIDER(2));
/* Enable IP clock */
CLK_EnableModuleClock(USBD_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_UART_CLK_DIVIDER(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PA_H_MFP &= ~( SYS_PA_H_MFP_PA15_MFP_Msk | SYS_PA_H_MFP_PA14_MFP_Msk);
SYS->PA_H_MFP |= (SYS_PA_H_MFP_PA15_MFP_UART0_TX|SYS_PA_H_MFP_PA14_MFP_UART0_RX);
/* Lock protected registers */
SYS_LockReg();
}
int main()
{
/* Unlock protected register */
SYS_UnlockReg();
SYS_Init();
UART_Init();
printf("\n\n");
printf("M451 FMC IAP Sample Code [LDROM code]\n");
/* Enable FMC ISP function */
FMC_Open();
printf("\n\nPress any key to branch to APROM...\n");
getchar();
printf("\n\nChange VECMAP and branch to LDROM...\n");
UART_WAIT_TX_EMPTY(UART0);
/* Mask all interrupt before changing VECMAP to avoid wrong interrupt handler fetched */
__set_PRIMASK(1);
/* Change VECMAP for booting to APROM */
FMC_SetVectorPageAddr(FMC_APROM_BASE);
/* Lock protected Register */
SYS_LockReg();
/* Software reset to boot to APROM */
NVIC_SystemReset();
while(1);
}
/*---------------------------------------------------------------------------------------------------------*/
int main(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
/* Init UART1 for testing */
UART1_Init();
/*---------------------------------------------------------------------------------------------------------*/
/* SAMPLE CODE */
/*---------------------------------------------------------------------------------------------------------*/
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
printf("\n\nUART Sample Program\n");
/* UART RS485 sample master function */
RS485_FunctionTest();
while(1);
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External LXT (32 kHz) */
CLK->PWRCTL |= CLK_PWRCTL_LXT_EN_Msk;
/* Waiting for LXT clock ready */
while(CLK_WaitClockReady( CLK_CLKSTATUS_LXT_STB_Msk) != 1);
CLK->APBCLK |= CLK_APBCLK_TMR0_EN_Msk | CLK_APBCLK_UART0_EN_Msk;
/* Select Timer clock source from LIRC */
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_TMR0_S_Msk) | CLK_CLKSEL1_TMR0_S_LXT;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and CycylesPerUs automatically. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
SYS->PB_L_MFP &= ~(SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB1_MFP_UART0_TX | SYS_PB_L_MFP_PB0_MFP_UART0_RX);
/* Lock protected registers */
SYS_LockReg();
}
int32_t main (void)
{
/* Init System, IP clock and multi-function I/O
In the end of SYS_Init() will issue SYS_LockReg()
to lock protected register. If user want to write
protected register, please issue SYS_UnlockReg()
to unlock protected register if necessary */
SYS_Init();
/* Init UART to 115200-8n1 for print message */
UART_Open(UART0, 115200);
printf("\nThis sample code demonstrate using WDT in polling mode\n");
// WDT register is locked, so it is necessary to unlock protect register before configure WDT
SYS_UnlockReg();
// WDT timeout every 2^14 WDT clock, disable system reset, disable wake up system
WDT_Open(WDT_TIMEOUT_2POW14, 0, FALSE, FALSE);
while(1) {
// WDT timeout flag set
if(WDT_GET_TIMEOUT_INT_FLAG()) {
// Reset WDT and clear time out flag
WDT_CLEAR_TIMEOUT_INT_FLAG();
printf("Reset WDT counter\n");
}
}
}
int main(void)
{
int i = 0;
/* Init System, IP clock and multi-function I/O
In the end of SYS_Init() will issue SYS_LockReg()
to lock protected register. If user want to write
protected register, please issue SYS_UnlockReg()
to unlock protected register if necessary */
SYS_Init();
/* Init UART to 115200-8n1 for print message */
UART_Open(UART0, 115200);
/*Initial Timer0 to periodic mode with 1Hz */
TIMER_Open(TIMER0, TIMER_PERIODIC_MODE, 1);
/* Enable timer wake up system */
TIMER_EnableWakeup(TIMER0);
/* Enable Timer0 interrupt */
TIMER_EnableInt(TIMER0);
NVIC_EnableIRQ(TMR0_IRQn);
/* Start Timer0 counting */
TIMER_Start(TIMER0);
/* Unlock protected registers */
SYS_UnlockReg();
while(1)
{
CLK_PowerDown();
printf("Wake %d\n", i++);
}
}
// ---------------------------------------------------------------------------------------
// Gas ADC initialize setting
// Set PB2 as ADC converter
// Select APB0/8 as ADC module clock source
// ---------------------------------------------------------------------------------------
void ID_Init()
{
SYS_UnlockReg();
/* Enable EADC module clock */
CLK_EnableModuleClock(EADC_MODULE);
/* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
SYS_LockReg();
/* Configure the GPB0 - GPB3 ADC analog input pins. */
SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB0MFP_Msk;
SYS->GPB_MFPL |= SYS_GPB_MFPL_PB0MFP_EADC_CH0;
GPIO_DISABLE_DIGITAL_PATH(PB, BIT0);
/* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */
EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END);
EADC_SetInternalSampleTime(EADC, 6);
/* Configure the sample module 0 for analog input channel 1 and software trigger source.*/
EADC_ConfigSampleModule(EADC, 0, EADC_SOFTWARE_TRIGGER, 0);
/* Clear the A/D ADINT0 interrupt flag for safe */
EADC_CLR_INT_FLAG(EADC, 0x1);
/* Enable the sample module 0 interrupt. */
EADC_ENABLE_INT(EADC, 0x1);//Enable sample module A/D ADINT0 interrupt.
EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 0, 0x1);//Enable sample module 0 interrupt.
}
void SPIClass::begin() {
if(init_flag==0) init();
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable IP clock */
CLK_EnableModuleClock(module);
/* Select IP clock source and clock divider */
CLK_SetModuleClock(module,clksel,0);
/* Lock protected registers */
SYS_LockReg();
/* Configure as a master, clock idle low, falling clock edge Tx, rising edge Rx and 8-bit transaction */
/* Set IP clock divider. SPI clock rate = 4MHz */
SPI_Open(spi, SPI_MASTER, SPI_MODE_0, 8, 4000000);
#if defined(__NUC240__) | defined(__NANO100__) | defined(__NUC131__)
SPI_EnableFIFO(spi,12,12);
#endif
setBitOrder(SS, MSBFIRST);
#if defined(__M451__)
SPI_ClearRxFIFO(spi);
SPI_TRIGGER(spi);
#endif
}
