/**
* @brief Device Initialization
* @param pdev: device instance
* @retval : None
*/
void DCD_Init(USB_CORE_HANDLE *pdev)
{
/*Device is in Default State*/
pdev->dev.device_status = USB_DEFAULT;
pdev->dev.device_address = 0;
pdev->dev.speed = USB_SPEED_FULL; /*kept for API compatibility reason*/
/*CNTR_FRES = 1*/
SetCNTR(CNTR_FRES);
/*CNTR_FRES = 0*/
SetCNTR(0);
/*Clear pending interrupts*/
SetISTR(0);
/*Set Btable Adress*/
SetBTABLE(BTABLE_ADDRESS);
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = CNTR_CTRM | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM | CNTR_SOFM \
| CNTR_ESOFM | CNTR_RESETM;
/*Set interrupt mask*/
SetCNTR(wInterrupt_Mask);
}
vsf_err_t stm32_usbd_fini(void)
{
// reset
SetCNTR(CNTR_FRES);
SetISTR(0);
SetCNTR(CNTR_FRES + CNTR_PDWN);
return VSFERR_NONE;
}
vsf_err_t stm32_usbd_init(void)
{
struct stm32_info_t *stm32_info;
memset(stm32_usbd_IN_epsize, 0, sizeof(stm32_usbd_IN_epsize));
memset(stm32_usbd_OUT_epsize, 0, sizeof(stm32_usbd_OUT_epsize));
memset(stm32_usbd_IN_dbuffer, 0, sizeof(stm32_usbd_IN_dbuffer));
memset(stm32_usbd_OUT_dbuffer, 0, sizeof(stm32_usbd_OUT_dbuffer));
memset(stm32_usbd_epaddr, -1, sizeof(stm32_usbd_epaddr));
if (stm32_interface_get_info(&stm32_info))
{
return VSFERR_FAIL;
}
switch (stm32_info->sys_freq_hz)
{
case 72 * 1000 * 1000:
RCC->CFGR &= ~STM32_RCC_CFGR_USBPRE;
break;
case 48 * 1000 * 1000:
RCC->CFGR |= STM32_RCC_CFGR_USBPRE;
break;
default:
return VSFERR_INVALID_PARAMETER;
}
RCC->APB1ENR |= STM32_RCC_APB1ENR_USBEN;
// reset
SetCNTR(CNTR_FRES);
SetCNTR(0);
// It seems that there MUST be at least 8 clock cycles
// between clear FRES and clear ISTR, or RESET flash can't be cleared
__asm("nop");
__asm("nop");
__asm("nop");
__asm("nop");
__asm("nop");
__asm("nop");
__asm("nop");
SetISTR(0);
SetCNTR(CNTR_CTRM | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM | CNTR_RESETM);
SetBTABLE(0);
return VSFERR_NONE;
}
