void Mapper090::SetBank_VRAM()
{
INT bank[4];
for( INT i = 0; i < 4; i++ ) {
bank[i] = ((INT)nth_reg[i]<<8)|((INT)ntl_reg[i]);
}
if( !patch && mir_mode ) {
for( INT i = 0; i < 4; i++ ) {
if( !nth_reg[i] && (ntl_reg[i] == (BYTE)i) ) {
mir_mode = 0;
}
}
if( mir_mode ) {
SetVROM_1K_Bank( 8, bank[0] );
SetVROM_1K_Bank( 9, bank[1] );
SetVROM_1K_Bank( 10, bank[2] );
SetVROM_1K_Bank( 11, bank[3] );
}
} else {
if( mir_type == 0 ) {
SetVRAM_Mirror( VRAM_VMIRROR );
} else
if( mir_type == 1 ) {
SetVRAM_Mirror( VRAM_HMIRROR );
} else {
SetVRAM_Mirror( VRAM_MIRROR4L );
}
}
}
void Mapper112::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
reg[0] = data;
SetBank_CPU();
SetBank_PPU();
break;
case 0xA000:
reg[1] = data;
switch( reg[0] & 0x07 ) {
case 0x00:
prg0 = (data&(PROM_8K_SIZE-1));
SetBank_CPU();
break;
case 0x01:
prg1 = (data&(PROM_8K_SIZE-1));
SetBank_CPU();
break;
case 0x02:
chr01 = data & 0xFE;
SetBank_PPU();
break;
case 0x03:
chr23 = data & 0xFE;
SetBank_PPU();
break;
case 0x04:
chr4 = data;
SetBank_PPU();
break;
case 0x05:
chr5 = data;
SetBank_PPU();
break;
case 0x06:
chr6 = data;
SetBank_PPU();
break;
case 0x07:
chr7 = data;
SetBank_PPU();
break;
}
break;
case 0xC000:
reg[3] = data;
SetBank_PPU();
case 0xE000:
reg[2] = data;
if( !nes->rom->Is4SCREEN() ) {
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
}
SetBank_PPU();
break;
}
}
void Mapper075::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0x8000:
SetPROM_8K_Bank( 4, data );
break;
case 0x9000:
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
reg[0] = (reg[0] & 0x0F) | ((data & 0x02) << 3);
reg[1] = (reg[1] & 0x0F) | ((data & 0x04) << 2);
SetVROM_4K_Bank( 0, reg[0] );
SetVROM_4K_Bank( 4, reg[1] );
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
case 0xC000:
SetPROM_8K_Bank( 6, data );
break;
case 0xE000:
reg[0] = (reg[0] & 0x10) | (data & 0x0F);
SetVROM_4K_Bank( 0, reg[0] );
break;
case 0xF000:
reg[1] = (reg[1] & 0x10) | (data & 0x0F);
SetVROM_4K_Bank( 4, reg[1] );
break;
}
}
void Mapper007::Write( WORD addr, BYTE data )
{
SetPROM_32K_Bank( data & 0x07 );
if( !patch ) {
if( data & 0x10 ) SetVRAM_Mirror( VRAM_MIRROR4H );
else SetVRAM_Mirror( VRAM_MIRROR4L );
}
}
// Famicom Jump 2
void Mapper016::WriteSubB( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
case 0x8001:
case 0x8002:
case 0x8003:
reg[0] = data & 0x01;
SetPROM_8K_Bank( 4, reg[0]*0x20+reg[2]*2+0 );
SetPROM_8K_Bank( 5, reg[0]*0x20+reg[2]*2+1 );
break;
case 0x8004:
case 0x8005:
case 0x8006:
case 0x8007:
reg[1] = data & 0x01;
SetPROM_8K_Bank( 6, reg[1]*0x20+0x1E );
SetPROM_8K_Bank( 7, reg[1]*0x20+0x1F );
break;
case 0x8008:
reg[2] = data;
SetPROM_8K_Bank( 4, reg[0]*0x20+reg[2]*2+0 );
SetPROM_8K_Bank( 5, reg[0]*0x20+reg[2]*2+1 );
SetPROM_8K_Bank( 6, reg[1]*0x20+0x1E );
SetPROM_8K_Bank( 7, reg[1]*0x20+0x1F );
break;
case 0x8009:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x800A:
irq_enable = data & 0x01;
irq_counter = irq_latch;
// if( !irq_enable ) {
// nes->cpu->ClrIRQ( IRQ_MAPPER );
// }
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x800B:
irq_latch = (irq_latch & 0xFF00) | data;
break;
case 0x800C:
irq_latch = ((INT)data << 8) | (irq_latch & 0x00FF);
break;
case 0x800D:
break;
}
}
void Mapper015::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
if( data&0x80 ) {
SetPROM_8K_Bank( 4, (data&0x3F)*2+1 );
SetPROM_8K_Bank( 5, (data&0x3F)*2+0 );
SetPROM_8K_Bank( 6, (data&0x3F)*2+3 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+2 );
} else {
SetPROM_8K_Bank( 4, (data&0x3F)*2+0 );
SetPROM_8K_Bank( 5, (data&0x3F)*2+1 );
SetPROM_8K_Bank( 6, (data&0x3F)*2+2 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+3 );
}
if( data&0x40 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
case 0x8001:
if( data&0x80 ) {
SetPROM_8K_Bank( 6, (data&0x3F)*2+1 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+0 );
} else {
SetPROM_8K_Bank( 6, (data&0x3F)*2+0 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+1 );
}
break;
case 0x8002:
if( data&0x80 ) {
SetPROM_8K_Bank( 4, (data&0x3F)*2+1 );
SetPROM_8K_Bank( 5, (data&0x3F)*2+1 );
SetPROM_8K_Bank( 6, (data&0x3F)*2+1 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+1 );
} else {
SetPROM_8K_Bank( 4, (data&0x3F)*2+0 );
SetPROM_8K_Bank( 5, (data&0x3F)*2+0 );
SetPROM_8K_Bank( 6, (data&0x3F)*2+0 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+0 );
}
break;
case 0x8003:
if( data&0x80 ) {
SetPROM_8K_Bank( 6, (data&0x3F)*2+1 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+0 );
} else {
SetPROM_8K_Bank( 6, (data&0x3F)*2+0 );
SetPROM_8K_Bank( 7, (data&0x3F)*2+1 );
}
if( data&0x40 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
}
}
void Mapper022::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
SetPROM_8K_Bank( 4, data );
break;
case 0x9000:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4H );
else SetVRAM_Mirror( VRAM_MIRROR4L );
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
case 0xB000:
SetVROM_1K_Bank( 0, data>>1 );
break;
case 0xB001:
SetVROM_1K_Bank( 1, data>>1 );
break;
case 0xC000:
SetVROM_1K_Bank( 2, data>>1 );
break;
case 0xC001:
SetVROM_1K_Bank( 3, data>>1 );
break;
case 0xD000:
SetVROM_1K_Bank( 4, data>>1 );
break;
case 0xD001:
SetVROM_1K_Bank( 5, data>>1 );
break;
case 0xE000:
SetVROM_1K_Bank( 6, data>>1 );
break;
case 0xE001:
SetVROM_1K_Bank( 7, data>>1 );
break;
}
}
void Mapper058::Write( WORD addr, BYTE data )
{
if( addr & 0x40 ) {
SetPROM_16K_Bank( 4, addr&0x07 );
SetPROM_16K_Bank( 6, addr&0x07 );
} else {
SetPROM_32K_Bank( (addr&0x06)>>1 );
}
if( VROM_1K_SIZE ) {
SetVROM_8K_Bank( (addr&0x38)>>3 );
}
if( data & 0x02 ) SetVRAM_Mirror( VRAM_VMIRROR );
else SetVRAM_Mirror( VRAM_HMIRROR );
}
void Mapper071::Write( WORD addr, BYTE data )
{
switch( addr&0xF000 ) {
case 0x9000:
if( data&0x10 ) SetVRAM_Mirror( VRAM_MIRROR4H );
else SetVRAM_Mirror( VRAM_MIRROR4L );
break;
case 0xC000:
case 0xD000:
case 0xE000:
case 0xF000:
SetPROM_16K_Bank( 4, data );
break;
}
}
void MapperUNL_KS7008::Reset()
{
SetPrg8r(1,0x6000,0);
SetPrg32r(2,0x8000,0);
SetVRAM_Mirror( VRAM_VMIRROR );
}
void Mapper135::WriteLow( WORD addr, BYTE data )
{
switch( addr & 0x4101 ) {
case 0x4100:
cmd = data & 0x07;
break;
case 0x4101:
switch( cmd ) {
case 0:
chr0l = data & 0x07;
SetBank_PPU();
break;
case 1:
chr0h = data & 0x07;
SetBank_PPU();
break;
case 2:
chr1l = data & 0x07;
SetBank_PPU();
break;
case 3:
chr1h = data & 0x07;
SetBank_PPU();
break;
case 4:
chrch = data & 0x07;
SetBank_PPU();
break;
case 5:
SetPROM_32K_Bank( data&0x07 );
break;
case 6:
break;
case 7:
switch( (data>>1)&0x03 ) {
case 0: SetVRAM_Mirror( VRAM_MIRROR4L ); break;
case 1: SetVRAM_Mirror( VRAM_HMIRROR ); break;
case 2: SetVRAM_Mirror( VRAM_VMIRROR ); break;
case 3: SetVRAM_Mirror( VRAM_MIRROR4L ); break;
}
break;
}
break;
}
CPU_MEM_BANK[addr>>13][addr&0x1FFF] = data;
}
void Mapper032::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0x8000:
if( reg & 0x02 ) {
SetPROM_8K_Bank( 6, data );
} else {
SetPROM_8K_Bank( 4, data );
}
break;
case 0x9000:
reg = data;
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
}
switch( addr & 0xF007 ) {
case 0xB000:
case 0xB001:
case 0xB002:
case 0xB003:
case 0xB004:
case 0xB005:
SetVROM_1K_Bank( addr & 0x0007, data );
break;
case 0xB006:
SetVROM_1K_Bank( 6, data );
if( patch && (data & 0x40) ) {
SetVRAM_Mirror( 0, 0, 0, 1 );
}
break;
case 0xB007:
SetVROM_1K_Bank( 7, data );
if( patch && (data & 0x40) ) {
SetVRAM_Mirror( 0, 0, 0, 0 );
}
break;
}
}
void MapperUNL_KS7037::Sync()
{
SetPROM_8K_Bank(4,reg[6]);//8000~9FFF
SetPROM_8K_Bank(6,reg[7]);//C000~DFFF
SetPROM_8K_Bank(7,PROM_8K_SIZE-1);//E000~FFFF
SetVROM_8K_Bank( 0 );
SetVRAM_Mirror(reg[2]&1,reg[4]&1,reg[3]&1,reg[5]&1);
}
void Mapper236::Write( WORD addr, BYTE data )
{
if( addr >= 0x8000 && addr <= 0xBFFF ) {
bank = ((addr&0x03)<<4)|(bank&0x07);
} else {
bank = (addr&0x07)|(bank&0x30);
mode = addr&0x30;
}
if( addr & 0x20 ) {
SetVRAM_Mirror( VRAM_HMIRROR );
} else {
SetVRAM_Mirror( VRAM_VMIRROR );
}
switch( mode ) {
case 0x00:
bank |= 0x08;
SetPROM_8K_Bank( 4, bank*2+0 );
SetPROM_8K_Bank( 5, bank*2+1 );
SetPROM_8K_Bank( 6, (bank|0x07)*2+0 );
SetPROM_8K_Bank( 7, (bank|0x07)*2+1 );
break;
case 0x10:
bank |= 0x37;
SetPROM_8K_Bank( 4, bank*2+0 );
SetPROM_8K_Bank( 5, bank*2+1 );
SetPROM_8K_Bank( 6, (bank|0x07)*2+0 );
SetPROM_8K_Bank( 7, (bank|0x07)*2+1 );
break;
case 0x20:
bank |= 0x08;
SetPROM_8K_Bank( 4, (bank&0xFE)*2+0 );
SetPROM_8K_Bank( 5, (bank&0xFE)*2+1 );
SetPROM_8K_Bank( 6, (bank&0xFE)*2+2 );
SetPROM_8K_Bank( 7, (bank&0xFE)*2+3 );
break;
case 0x30:
bank |= 0x08;
SetPROM_8K_Bank( 4, bank*2+0 );
SetPROM_8K_Bank( 5, bank*2+1 );
SetPROM_8K_Bank( 6, bank*2+0 );
SetPROM_8K_Bank( 7, bank*2+1 );
break;
}
}
void Mapper061::Write( WORD addr, BYTE data )
{
switch( addr & 0x30 ) {
case 0x00:
case 0x30:
SetPROM_32K_Bank( addr & 0x0F );
break;
case 0x10:
case 0x20:
SetPROM_16K_Bank( 4, ((addr & 0x0F)<<1)|((addr&0x20)>>4) );
SetPROM_16K_Bank( 6, ((addr & 0x0F)<<1)|((addr&0x20)>>4) );
break;
}
if( addr & 0x80 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
}
void Mapper175::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
if( data & 0x04 ) {
SetVRAM_Mirror( VRAM_HMIRROR );
} else {
SetVRAM_Mirror( VRAM_VMIRROR );
}
break;
case 0xA000:
reg_dat = data;
SetPROM_8K_Bank( 7, (reg_dat & 0x0F)*2+1 );
SetVROM_8K_Bank( reg_dat & 0x0F );
break;
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper046 Rumble Station //
//////////////////////////////////////////////////////////////////////////
void Mapper046::Reset()
{
reg[0] = 0;
reg[1] = 0;
reg[2] = 0;
reg[3] = 0;
SetBank();
SetVRAM_Mirror( VRAM_VMIRROR );
}
void Mapper114::Write( WORD addr, BYTE data )
{
if( addr == 0xE003 ) {
irq_counter = data;
} else
if( addr == 0xE002 ) {
irq_occur = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
} else {
switch( addr & 0xE000 ) {
case 0x8000:
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
case 0xA000:
reg_c = 1;
reg_a = data;
break;
case 0xC000:
if( !reg_c ) {
break;
}
reg_b[reg_a&0x07] = data;
switch( reg_a & 0x07 ) {
case 0:
case 1:
case 2:
case 3:
case 6:
case 7:
SetBank_PPU();
break;
case 4:
case 5:
SetBank_CPU();
break;
}
reg_c = 0;
break;
}
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper255 110-in-1 //
//////////////////////////////////////////////////////////////////////////
void Mapper255::Reset()
{
SetPROM_32K_Bank( 0 );
SetVROM_8K_Bank( 0 );
SetVRAM_Mirror( VRAM_VMIRROR );
reg[0] = 0;
reg[1] = 0;
reg[2] = 0;
reg[3] = 0;
}
void Mapper191::WriteLow( WORD addr, BYTE data )
{
switch( addr ) {
case 0x4100:
reg[0]=data;
break;
case 0x4101:
reg[1]=data;
switch( reg[0] ) {
case 0:
chr0=data&7;
SetBank_PPU();
break;
case 1:
chr1=data&7;
SetBank_PPU();
break;
case 2:
chr2=data&7;
SetBank_PPU();
break;
case 3:
chr3=data&7;
SetBank_PPU();
break;
case 4:
highbank=data&7;
SetBank_PPU();
break;
case 5:
prg0=data&7;
SetBank_CPU();
break;
case 7:
if( data & 0x02 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
}
break;
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper251 //
//////////////////////////////////////////////////////////////////////////
void Mapper251::Reset()
{
SetPROM_32K_Bank( 0, 1, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
SetVRAM_Mirror( VRAM_VMIRROR );
INT i;
for( i = 0; i < 11; i++ )
reg[i] = 0;
for( i = 0; i < 4; i++ )
breg[i] = 0;
}
void Mapper113::WriteLow( WORD addr, BYTE data )
{
//DEBUGOUT( "$%04X:$%02X L=%3d\n", addr, data, nes->GetScanline() );
switch( addr ) {
case 0x4100:
case 0x4111:
case 0x4120:
case 0x4194:
case 0x4195:
case 0x4900:
if( nes->rom->GetPROM_CRC() == 0xA75AEDE5 ) { // HES 6-in-1
if( data & 0x80 ) {
SetVRAM_Mirror( VRAM_VMIRROR );
} else {
SetVRAM_Mirror( VRAM_HMIRROR );
}
}
SetPROM_32K_Bank( data >> 3 );
SetVROM_8K_Bank( ((data>>3)&0x08)+(data&0x07) );
break;
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper007 AOROM/AMROM //
//////////////////////////////////////////////////////////////////////////
void Mapper007::Reset()
{
patch = 0;
SetPROM_32K_Bank( 0 );
SetVRAM_Mirror( VRAM_MIRROR4L );
DWORD crc = nes->rom->GetPROM_CRC();
if( crc == 0x3c9fe649 ) { // WWF Wrestlemania Challenge(U)
SetVRAM_Mirror( VRAM_VMIRROR );
patch = 1;
}
if( crc == 0x09874777 ) { // Marble Madness(U)
nes->SetRenderMethod( NES::TILE_RENDER );
}
if( crc == 0x279710DC // Battletoads (U)
|| crc == 0xCEB65B06 ) { // Battletoads Double Dragon (U)
nes->SetRenderMethod( NES::PRE_ALL_RENDER );
::memset( WRAM, 0, sizeof(WRAM) );
}
}
void Mapper042::Write( WORD addr, BYTE data )
{
switch( addr & 0xE003 ) {
case 0xE000:
SetPROM_8K_Bank( 3, data&0x0F );
break;
case 0xE001:
if( data&0x08 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
case 0xE002:
if( data&0x02 ) {
irq_enable = 0xFF;
} else {
irq_enable = 0;
irq_counter = 0;
}
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
void Mapper009::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0xA000:
SetPROM_8K_Bank( 4, data );
break;
case 0xB000:
reg[0] = data;
if( latch_a == 0xFD ) {
SetVROM_4K_Bank( 0, reg[0] );
}
break;
case 0xC000:
reg[1] = data;
if( latch_a == 0xFE ) {
SetVROM_4K_Bank( 0, reg[1] );
}
break;
case 0xD000:
reg[2] = data;
if( latch_b == 0xFD ) {
SetVROM_4K_Bank( 4, reg[2] );
}
break;
case 0xE000:
reg[3] = data;
if( latch_b == 0xFE ) {
SetVROM_4K_Bank( 4, reg[3] );
}
break;
case 0xF000:
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
}
}
void Mapper113::Write( WORD addr, BYTE data )
{
//DEBUGOUT( "$%04X:$%02X L=%3d\n", addr, data, nes->GetScanline() );
switch( addr ) {
case 0x8008:
case 0x8009:
SetPROM_32K_Bank( data >> 3 );
SetVROM_8K_Bank( ((data>>3)&0x08)+(data&0x07) );
break;
case 0x8E66:
case 0x8E67:
SetVROM_8K_Bank( (data&0x07)?0:1 );
break;
case 0xE00A:
SetVRAM_Mirror( VRAM_MIRROR4L );
break;
}
}
void Mapper025::Write( WORD addr, BYTE data )
{
//if( addr >= 0xF000 )
//DEBUGOUT( "M25 WR $%04X=$%02X L=%3d\n", addr, data, nes->GetScanline() );
switch( addr & 0xF000 ) {
case 0x8000:
if(reg[10] & 0x02) {
reg[9] = data;
SetPROM_8K_Bank( 6, data );
} else {
reg[8] = data;
SetPROM_8K_Bank( 4, data );
}
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
}
switch( addr & 0xF00F ) {
case 0x9000:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x9001:
case 0x9004:
if((reg[10] & 0x02) != (data & 0x02)) {
BYTE swap = reg[8];
reg[8] = reg[9];
reg[9] = swap;
SetPROM_8K_Bank( 4, reg[8] );
SetPROM_8K_Bank( 6, reg[9] );
}
reg[10] = data;
break;
case 0xB000:
reg[0] = (reg[0] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB002:
case 0xB008:
reg[0] = (reg[0] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB001:
case 0xB004:
reg[1] = (reg[1] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xB003:
case 0xB00C:
reg[1] = (reg[1] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xC000:
reg[2] = (reg[2] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC002:
case 0xC008:
reg[2] = (reg[2] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC001:
case 0xC004:
reg[3] = (reg[3] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xC003:
case 0xC00C:
reg[3] = (reg[3] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xD000:
reg[4] = (reg[4] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD002:
case 0xD008:
reg[4] = (reg[4] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD001:
case 0xD004:
reg[5] = (reg[5] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xD003:
case 0xD00C:
reg[5] = (reg[5] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xE000:
reg[6] = (reg[6] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE002:
case 0xE008:
reg[6] = (reg[6] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE001:
case 0xE004:
reg[7] = (reg[7] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xE003:
case 0xE00C:
reg[7] = (reg[7] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xF000:
irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF002:
case 0xF008:
irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF001:
case 0xF004:
irq_enable = data & 0x03;
// irq_counter = 0x100 - irq_latch;
irq_counter = irq_latch;
irq_clock = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF003:
case 0xF00C:
irq_enable = (irq_enable & 0x01)*3;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
void Mapper004::Write( WORD addr, BYTE data )
{
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
switch( addr & 0xE001 ) {
case 0x8000:
reg[0] = data;
SetBank_CPU();
SetBank_PPU();
break;
case 0x8001:
reg[1] = data;
switch( reg[0] & 0x07 ) {
case 0x00:
chr01 = data & 0xFE;
SetBank_PPU();
break;
case 0x01:
chr23 = data & 0xFE;
SetBank_PPU();
break;
case 0x02:
chr4 = data;
SetBank_PPU();
break;
case 0x03:
chr5 = data;
SetBank_PPU();
break;
case 0x04:
chr6 = data;
SetBank_PPU();
break;
case 0x05:
chr7 = data;
SetBank_PPU();
break;
case 0x06:
prg0 = data;
SetBank_CPU();
break;
case 0x07:
prg1 = data;
SetBank_CPU();
break;
}
break;
case 0xA000:
reg[2] = data;
if( !nes->rom->Is4SCREEN() ) {
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
}
break;
case 0xA001:
reg[3] = data;
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
break;
case 0xC000:
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
reg[4] = data;
if( irq_type == MMC3_IRQ_KLAX || irq_type == MMC3_IRQ_ROCKMAN3 ) {
irq_counter = data;
} else {
irq_latch = data;
}
if( irq_type == MMC3_IRQ_DBZ2 ) {
irq_latch = 0x07;
}
break;
case 0xC001:
reg[5] = data;
if( irq_type == MMC3_IRQ_KLAX || irq_type == MMC3_IRQ_ROCKMAN3 ) {
irq_latch = data;
} else {
if( (nes->GetScanline() < 240) || (irq_type == MMC3_IRQ_SHOUGIMEIKAN) ) {
irq_counter |= 0x80;
irq_preset = 0xFF;
} else {
irq_counter |= 0x80;
irq_preset_vbl = 0xFF;
irq_preset = 0;
}
}
break;
case 0xE000:
reg[6] = data;
irq_enable = 0;
irq_request = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xE001:
reg[7] = data;
irq_enable = 1;
irq_request = 0;
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
void Mapper083::Write( WORD addr, BYTE data )
{
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
switch( addr ) {
case 0x8000:
case 0xB000:
case 0xB0FF:
case 0xB1FF:
reg[0] = data;
chr_bank = (data&0x30)<<4;
SetPROM_16K_Bank( 4, data );
SetPROM_16K_Bank( 6, (data&0x30)|0x0F );
break;
case 0x8100:
reg[1] = data & 0x80;
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x8200:
irq_counter = (irq_counter&0xFF00)|(INT)data;
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x8201:
irq_counter = (irq_counter&0x00FF)|((INT)data<<8);
irq_enable = reg[1];
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x8300:
SetPROM_8K_Bank( 4, data );
break;
case 0x8301:
SetPROM_8K_Bank( 5, data );
break;
case 0x8302:
SetPROM_8K_Bank( 6, data );
break;
case 0x8310:
if( patch ) {
SetVROM_2K_Bank( 0, chr_bank|data );
} else {
SetVROM_1K_Bank( 0, chr_bank|data );
}
break;
case 0x8311:
if( patch ) {
SetVROM_2K_Bank( 2, chr_bank|data );
} else {
SetVROM_1K_Bank( 1, chr_bank|data );
}
break;
case 0x8312:
SetVROM_1K_Bank( 2, chr_bank|data );
break;
case 0x8313:
SetVROM_1K_Bank( 3, chr_bank|data );
break;
case 0x8314:
SetVROM_1K_Bank( 4, chr_bank|data );
break;
case 0x8315:
SetVROM_1K_Bank( 5, chr_bank|data );
break;
case 0x8316:
if( patch ) {
SetVROM_2K_Bank( 4, chr_bank|data );
} else {
SetVROM_1K_Bank( 6, chr_bank|data );
}
break;
case 0x8317:
if( patch ) {
SetVROM_2K_Bank( 6, chr_bank|data );
} else {
SetVROM_1K_Bank( 7, chr_bank|data );
}
break;
case 0x8318:
SetPROM_16K_Bank( 4, (reg[0]&0x30)|data );
break;
}
}
// Normal mapper #16
void Mapper016::WriteSubA( WORD addr, BYTE data )
{
switch( addr & 0x000F ) {
case 0x0000:
case 0x0001:
case 0x0002:
case 0x0003:
case 0x0004:
case 0x0005:
case 0x0006:
case 0x0007:
if( VROM_1K_SIZE ) {
SetVROM_1K_Bank( addr&0x0007, data );
}
if( eeprom_type == 2 ) {
reg[0] = data;
x24c01.Write( (data&0x08)?0xFF:0, (reg[1]&0x40)?0xFF:0 );
}
break;
case 0x0008:
SetPROM_16K_Bank( 4, data );
break;
case 0x0009:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x000A:
irq_enable = data & 0x01;
irq_counter = irq_latch;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x000B:
irq_latch = (irq_latch & 0xFF00) | data;
irq_counter = (irq_counter & 0xFF00) | data;
break;
case 0x000C:
irq_latch = ((INT)data << 8) | (irq_latch & 0x00FF);
irq_counter = ((INT)data << 8) | (irq_counter & 0x00FF);
break;
case 0x000D:
// EEPTYPE0(DragonBallZ)
if( eeprom_type == 0 ) {
x24c01.Write( (data&0x20)?0xFF:0, (data&0x40)?0xFF:0 );
}
// EEPTYPE1(DragonBallZ2,Z3,Z Gaiden)
if( eeprom_type == 1 ) {
x24c02.Write( (data&0x20)?0xFF:0, (data&0x40)?0xFF:0 );
}
// EEPTYPE2(DATACH)
if( eeprom_type == 2 ) {
reg[1] = data;
x24c02.Write( (data&0x20)?0xFF:0, (data&0x40)?0xFF:0 );
x24c01.Write( (reg[0]&0x08)?0xFF:0, (data&0x40)?0xFF:0 );
}
break;
}
}
