void SetVROM_4K_Bank( BYTE page, INT bank ) { SetVROM_1K_Bank( page+0, bank*4+0 ); SetVROM_1K_Bank( page+1, bank*4+1 ); SetVROM_1K_Bank( page+2, bank*4+2 ); SetVROM_1K_Bank( page+3, bank*4+3 ); }
void Mapper090::SetBank_VRAM() { INT bank[4]; for( INT i = 0; i < 4; i++ ) { bank[i] = ((INT)nth_reg[i]<<8)|((INT)ntl_reg[i]); } if( !patch && mir_mode ) { for( INT i = 0; i < 4; i++ ) { if( !nth_reg[i] && (ntl_reg[i] == (BYTE)i) ) { mir_mode = 0; } } if( mir_mode ) { SetVROM_1K_Bank( 8, bank[0] ); SetVROM_1K_Bank( 9, bank[1] ); SetVROM_1K_Bank( 10, bank[2] ); SetVROM_1K_Bank( 11, bank[3] ); } } else { if( mir_type == 0 ) { SetVRAM_Mirror( VRAM_VMIRROR ); } else if( mir_type == 1 ) { SetVRAM_Mirror( VRAM_HMIRROR ); } else { SetVRAM_Mirror( VRAM_MIRROR4L ); } } }
void Mapper033::SetBank() { SetVROM_2K_Bank( 0, reg[0] ); SetVROM_2K_Bank( 2, reg[1] ); // if( reg[6] & 0x01 ) { SetVROM_1K_Bank( 4, reg[2] ); SetVROM_1K_Bank( 5, reg[3] ); SetVROM_1K_Bank( 6, reg[4] ); SetVROM_1K_Bank( 7, reg[5] ); // } else { // SetVROM_2K_Bank( 4, reg[0] ); // SetVROM_2K_Bank( 6, reg[1] ); // } }
void Mapper032::Write( WORD addr, BYTE data ) { switch( addr & 0xF000 ) { case 0x8000: if( reg & 0x02 ) { SetPROM_8K_Bank( 6, data ); } else { SetPROM_8K_Bank( 4, data ); } break; case 0x9000: reg = data; if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR ); else SetVRAM_Mirror( VRAM_VMIRROR ); break; case 0xA000: SetPROM_8K_Bank( 5, data ); break; } switch( addr & 0xF007 ) { case 0xB000: case 0xB001: case 0xB002: case 0xB003: case 0xB004: case 0xB005: SetVROM_1K_Bank( addr & 0x0007, data ); break; case 0xB006: SetVROM_1K_Bank( 6, data ); if( patch && (data & 0x40) ) { SetVRAM_Mirror( 0, 0, 0, 1 ); } break; case 0xB007: SetVROM_1K_Bank( 7, data ); if( patch && (data & 0x40) ) { SetVRAM_Mirror( 0, 0, 0, 0 ); } break; } }
void SetVROM_8K_Bank( INT bank0, INT bank1, INT bank2, INT bank3, INT bank4, INT bank5, INT bank6, INT bank7 ) { SetVROM_1K_Bank( 0, bank0 ); SetVROM_1K_Bank( 1, bank1 ); SetVROM_1K_Bank( 2, bank2 ); SetVROM_1K_Bank( 3, bank3 ); SetVROM_1K_Bank( 4, bank4 ); SetVROM_1K_Bank( 5, bank5 ); SetVROM_1K_Bank( 6, bank6 ); SetVROM_1K_Bank( 7, bank7 ); }
void Mapper074::SetBank_PPUSUB( int bank, int page ) { if( !patch && (page == 8 || page == 9) ) { SetCRAM_1K_Bank( bank, page & 7 ); } else if( patch == 1 && page >= 128 ) { SetCRAM_1K_Bank( bank, page & 7 ); } else { SetVROM_1K_Bank( bank, page ); } }
void Mapper191::SetBank_PPU() { if( VROM_1K_SIZE ) { SetVROM_1K_Bank( 0, (((highbank<<3)+chr0)<<2)+0 ); SetVROM_1K_Bank( 1, (((highbank<<3)+chr0)<<2)+1 ); SetVROM_1K_Bank( 2, (((highbank<<3)+chr1)<<2)+2 ); SetVROM_1K_Bank( 3, (((highbank<<3)+chr1)<<2)+3 ); SetVROM_1K_Bank( 4, (((highbank<<3)+chr2)<<2)+0 ); SetVROM_1K_Bank( 5, (((highbank<<3)+chr2)<<2)+1 ); SetVROM_1K_Bank( 6, (((highbank<<3)+chr3)<<2)+2 ); SetVROM_1K_Bank( 7, (((highbank<<3)+chr3)<<2)+3 ); } }
void Mapper046::SetBank() { SetPROM_8K_Bank( 4, reg[0]*8+reg[2]*4+0 ); SetPROM_8K_Bank( 5, reg[0]*8+reg[2]*4+1 ); SetPROM_8K_Bank( 6, reg[0]*8+reg[2]*4+2 ); SetPROM_8K_Bank( 7, reg[0]*8+reg[2]*4+3 ); SetVROM_1K_Bank( 0, reg[1]*64+reg[3]*8+0 ); SetVROM_1K_Bank( 1, reg[1]*64+reg[3]*8+1 ); SetVROM_1K_Bank( 2, reg[1]*64+reg[3]*8+2 ); SetVROM_1K_Bank( 3, reg[1]*64+reg[3]*8+3 ); SetVROM_1K_Bank( 4, reg[1]*64+reg[3]*8+4 ); SetVROM_1K_Bank( 5, reg[1]*64+reg[3]*8+5 ); SetVROM_1K_Bank( 6, reg[1]*64+reg[3]*8+6 ); SetVROM_1K_Bank( 7, reg[1]*64+reg[3]*8+7 ); }
void Mapper117::Write( WORD addr, BYTE data ) { switch( addr ) { case 0x8000: SetPROM_8K_Bank( 4, data ); break; case 0x8001: SetPROM_8K_Bank( 5, data ); break; case 0x8002: SetPROM_8K_Bank( 6, data ); break; case 0xA000: SetVROM_1K_Bank( 0, data ); break; case 0xA001: SetVROM_1K_Bank( 1, data ); break; case 0xA002: SetVROM_1K_Bank( 2, data ); break; case 0xA003: SetVROM_1K_Bank( 3, data ); break; case 0xA004: SetVROM_1K_Bank( 4, data ); break; case 0xA005: SetVROM_1K_Bank( 5, data ); break; case 0xA006: SetVROM_1K_Bank( 6, data ); break; case 0xA007: SetVROM_1K_Bank( 7, data ); break; case 0xC001: case 0xC002: case 0xC003: irq_counter = data; break; case 0xE000: irq_enable = data & 1; // nes->cpu->ClrIRQ( IRQ_MAPPER ); break; } }
// Normal mapper #16 void Mapper016::WriteSubA( WORD addr, BYTE data ) { switch( addr & 0x000F ) { case 0x0000: case 0x0001: case 0x0002: case 0x0003: case 0x0004: case 0x0005: case 0x0006: case 0x0007: if( VROM_1K_SIZE ) { SetVROM_1K_Bank( addr&0x0007, data ); } if( eeprom_type == 2 ) { reg[0] = data; x24c01.Write( (data&0x08)?0xFF:0, (reg[1]&0x40)?0xFF:0 ); } break; case 0x0008: SetPROM_16K_Bank( 4, data ); break; case 0x0009: data &= 0x03; if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR ); else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR ); else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L ); else SetVRAM_Mirror( VRAM_MIRROR4H ); break; case 0x000A: irq_enable = data & 0x01; irq_counter = irq_latch; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0x000B: irq_latch = (irq_latch & 0xFF00) | data; irq_counter = (irq_counter & 0xFF00) | data; break; case 0x000C: irq_latch = ((INT)data << 8) | (irq_latch & 0x00FF); irq_counter = ((INT)data << 8) | (irq_counter & 0x00FF); break; case 0x000D: // EEPTYPE0(DragonBallZ) if( eeprom_type == 0 ) { x24c01.Write( (data&0x20)?0xFF:0, (data&0x40)?0xFF:0 ); } // EEPTYPE1(DragonBallZ2,Z3,Z Gaiden) if( eeprom_type == 1 ) { x24c02.Write( (data&0x20)?0xFF:0, (data&0x40)?0xFF:0 ); } // EEPTYPE2(DATACH) if( eeprom_type == 2 ) { reg[1] = data; x24c02.Write( (data&0x20)?0xFF:0, (data&0x40)?0xFF:0 ); x24c01.Write( (reg[0]&0x08)?0xFF:0, (data&0x40)?0xFF:0 ); } break; } }
void Mapper064::Write( WORD addr, BYTE data ) { //DEBUGOUT( "$%04X:$%02X\n", addr, data ); switch( addr&0xF003 ) { case 0x8000: reg[0] = data&0x0F; reg[1] = data&0x40; reg[2] = data&0x80; break; case 0x8001: switch( reg[0] ) { case 0x00: if( reg[2] ) { SetVROM_1K_Bank( 4, data+0 ); SetVROM_1K_Bank( 5, data+1 ); } else { SetVROM_1K_Bank( 0, data+0 ); SetVROM_1K_Bank( 1, data+1 ); } break; case 0x01: if( reg[2] ) { SetVROM_1K_Bank( 6, data+0 ); SetVROM_1K_Bank( 7, data+1 ); } else { SetVROM_1K_Bank( 2, data+0 ); SetVROM_1K_Bank( 3, data+1 ); } break; case 0x02: if( reg[2] ) { SetVROM_1K_Bank( 0, data ); } else { SetVROM_1K_Bank( 4, data ); } break; case 0x03: if( reg[2] ) { SetVROM_1K_Bank( 1, data ); } else { SetVROM_1K_Bank( 5, data ); } break; case 0x04: if( reg[2] ) { SetVROM_1K_Bank( 2, data ); } else { SetVROM_1K_Bank( 6, data ); } break; case 0x05: if( reg[2] ) { SetVROM_1K_Bank( 3, data ); } else { SetVROM_1K_Bank( 7, data ); } break; case 0x06: if( reg[1] ) { SetPROM_8K_Bank( 5, data ); } else { SetPROM_8K_Bank( 4, data ); } break; case 0x07: if( reg[1] ) { SetPROM_8K_Bank( 6, data ); } else { SetPROM_8K_Bank( 5, data ); } break; case 0x08: SetVROM_1K_Bank( 1, data ); break; case 0x09: SetVROM_1K_Bank( 3, data ); break; case 0x0F: if( reg[1] ) { SetPROM_8K_Bank( 4, data ); } else { SetPROM_8K_Bank( 6, data ); } break; } break; case 0xA000: if( data&0x01 ) SetVRAM_Mirror( VRAM_HMIRROR ); else SetVRAM_Mirror( VRAM_VMIRROR ); break; case 0xC000: irq_latch = data; if( irq_reset ) { irq_counter = irq_latch; } break; case 0xC001: irq_reset = 0xFF; irq_counter = irq_latch; irq_mode = data & 0x01; break; case 0xE000: irq_enable = 0; if( irq_reset ) { irq_counter = irq_latch; } nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xE001: irq_enable = 0xFF; if( irq_reset ) { irq_counter = irq_latch; } break; } }
void Mapper119::SetBank_PPU() { if( reg[0]&0x80 ) { if( chr4&0x40 ) SetCRAM_1K_Bank( 0, chr4&0x07 ); else SetVROM_1K_Bank( 0, chr4 ); if( chr5&0x40 ) SetCRAM_1K_Bank( 1, chr5&0x07 ); else SetVROM_1K_Bank( 1, chr5 ); if( chr6&0x40 ) SetCRAM_1K_Bank( 2, chr6&0x07 ); else SetVROM_1K_Bank( 2, chr6 ); if( chr7&0x40 ) SetCRAM_1K_Bank( 3, chr7&0x07 ); else SetVROM_1K_Bank( 3, chr7 ); if( (chr01+0)&0x40 ) SetCRAM_1K_Bank( 4, (chr01+0)&0x07 ); else SetVROM_1K_Bank( 4, (chr01+0) ); if( (chr01+1)&0x40 ) SetCRAM_1K_Bank( 5, (chr01+1)&0x07 ); else SetVROM_1K_Bank( 5, (chr01+1) ); if( (chr23+0)&0x40 ) SetCRAM_1K_Bank( 6, (chr23+0)&0x07 ); else SetVROM_1K_Bank( 6, (chr23+0) ); if( (chr23+1)&0x40 ) SetCRAM_1K_Bank( 7, (chr23+1)&0x07 ); else SetVROM_1K_Bank( 7, (chr23+1) ); } else { if( (chr01+0)&0x40 ) SetCRAM_1K_Bank( 0, (chr01+0)&0x07 ); else SetVROM_1K_Bank( 0, (chr01+0) ); if( (chr01+1)&0x40 ) SetCRAM_1K_Bank( 1, (chr01+1)&0x07 ); else SetVROM_1K_Bank( 1, (chr01+1) ); if( (chr23+0)&0x40 ) SetCRAM_1K_Bank( 2, (chr23+0)&0x07 ); else SetVROM_1K_Bank( 2, (chr23+0) ); if( (chr23+1)&0x40 ) SetCRAM_1K_Bank( 3, (chr23+1)&0x07 ); else SetVROM_1K_Bank( 3, (chr23+1) ); if( chr4&0x40 ) SetCRAM_1K_Bank( 4, chr4&0x07 ); else SetVROM_1K_Bank( 4, chr4 ); if( chr5&0x40 ) SetCRAM_1K_Bank( 5, chr5&0x07 ); else SetVROM_1K_Bank( 5, chr5 ); if( chr6&0x40 ) SetCRAM_1K_Bank( 6, chr6&0x07 ); else SetVROM_1K_Bank( 6, chr6 ); if( chr7&0x40 ) SetCRAM_1K_Bank( 7, chr7&0x07 ); else SetVROM_1K_Bank( 7, chr7 ); } }
void Mapper065::Write( WORD addr, BYTE data ) { switch( addr ) { case 0x8000: SetPROM_8K_Bank( 4, data ); break; case 0x9000: if( !patch ) { if( data & 0x40 ) SetVRAM_Mirror( VRAM_VMIRROR ); else SetVRAM_Mirror( VRAM_HMIRROR ); } break; case 0x9001: if( patch ) { if( data & 0x80 ) SetVRAM_Mirror( VRAM_HMIRROR ); else SetVRAM_Mirror( VRAM_VMIRROR ); } break; case 0x9003: if( !patch ) { irq_enable = data & 0x80; nes->cpu->ClrIRQ( IRQ_MAPPER ); } break; case 0x9004: if( !patch ) { irq_counter = irq_latch; } break; case 0x9005: if( patch ) { irq_counter = (BYTE)(data<<1); irq_enable = data; nes->cpu->ClrIRQ( IRQ_MAPPER ); } else { irq_latch = (irq_latch & 0x00FF)|((INT)data<<8); } break; case 0x9006: if( patch ) { irq_enable = 1; } else { irq_latch = (irq_latch & 0xFF00)|data; } break; case 0xB000: case 0xB001: case 0xB002: case 0xB003: case 0xB004: case 0xB005: case 0xB006: case 0xB007: SetVROM_1K_Bank( addr & 0x0007, data ); break; case 0xA000: SetPROM_8K_Bank( 5, data ); break; case 0xC000: SetPROM_8K_Bank( 6, data ); break; } }
void Mapper252::Write( WORD addr, BYTE data ) { if( (addr & 0xF000) == 0x8000 ) { SetPROM_8K_Bank( 4, data ); return; } if( (addr & 0xF000) == 0xA000 ) { SetPROM_8K_Bank( 5, data ); return; } switch( addr & 0xF00C ) { case 0xB000: reg[0] = (reg[0] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 0, reg[0] ); break; case 0xB004: reg[0] = (reg[0] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 0, reg[0] ); break; case 0xB008: reg[1] = (reg[1] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 1, reg[1] ); break; case 0xB00C: reg[1] = (reg[1] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 1, reg[1] ); break; case 0xC000: reg[2] = (reg[2] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 2, reg[2] ); break; case 0xC004: reg[2] = (reg[2] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 2, reg[2] ); break; case 0xC008: reg[3] = (reg[3] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 3, reg[3] ); break; case 0xC00C: reg[3] = (reg[3] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 3, reg[3] ); break; case 0xD000: reg[4] = (reg[4] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 4, reg[4] ); break; case 0xD004: reg[4] = (reg[4] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 4, reg[4] ); break; case 0xD008: reg[5] = (reg[5] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 5, reg[5] ); break; case 0xD00C: reg[5] = (reg[5] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 5, reg[5] ); break; case 0xE000: reg[6] = (reg[6] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 6, reg[6] ); break; case 0xE004: reg[6] = (reg[6] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 6, reg[6] ); break; case 0xE008: reg[7] = (reg[7] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 7, reg[7] ); break; case 0xE00C: reg[7] = (reg[7] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 7, reg[7] ); break; case 0xF000: irq_latch = (irq_latch & 0xF0) | (data & 0x0F); irq_occur = 0; break; case 0xF004: irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4); irq_occur = 0; break; case 0xF008: irq_enable = data & 0x03; if( irq_enable & 0x02 ) { irq_counter = irq_latch; irq_clock = 0; } irq_occur = 0; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xF00C: irq_enable = (irq_enable & 0x01) * 3; irq_occur = 0; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; } }
void SetVROM_2K_Bank( BYTE page, INT bank ) { SetVROM_1K_Bank( page+0, bank*2+0 ); SetVROM_1K_Bank( page+1, bank*2+1 ); }
void Mapper069::Write( WORD addr, BYTE data ) { switch( addr & 0xE000 ) { case 0x8000: reg = data; break; case 0xA000: switch( reg & 0x0F ) { case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: SetVROM_1K_Bank( reg&0x07, data ); break; case 0x08: if( !patch && !(data & 0x40) ) { SetPROM_8K_Bank( 3, data ); } break; case 0x09: SetPROM_8K_Bank( 4, data ); break; case 0x0A: SetPROM_8K_Bank( 5, data ); break; case 0x0B: SetPROM_8K_Bank( 6, data ); break; case 0x0C: data &= 0x03; if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR ); else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR ); else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L ); else SetVRAM_Mirror( VRAM_MIRROR4H ); break; case 0x0D: irq_enable = data; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0x0E: irq_counter = (irq_counter & 0xFF00) | data; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0x0F: irq_counter = (irq_counter & 0x00FF) | (data << 8); nes->cpu->ClrIRQ( IRQ_MAPPER ); break; } break; case 0xC000: case 0xE000: nes->apu->ExWrite( addr, data ); break; } }
void SetVROM_8K_Bank( INT bank ) { for( INT i = 0; i < 8; i++ ) { SetVROM_1K_Bank( i, bank*8+i ); } }
void Mapper083::Write( WORD addr, BYTE data ) { //DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() ); switch( addr ) { case 0x8000: case 0xB000: case 0xB0FF: case 0xB1FF: reg[0] = data; chr_bank = (data&0x30)<<4; SetPROM_16K_Bank( 4, data ); SetPROM_16K_Bank( 6, (data&0x30)|0x0F ); break; case 0x8100: reg[1] = data & 0x80; data &= 0x03; if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR ); else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR ); else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L ); else SetVRAM_Mirror( VRAM_MIRROR4H ); break; case 0x8200: irq_counter = (irq_counter&0xFF00)|(INT)data; // nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0x8201: irq_counter = (irq_counter&0x00FF)|((INT)data<<8); irq_enable = reg[1]; // nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0x8300: SetPROM_8K_Bank( 4, data ); break; case 0x8301: SetPROM_8K_Bank( 5, data ); break; case 0x8302: SetPROM_8K_Bank( 6, data ); break; case 0x8310: if( patch ) { SetVROM_2K_Bank( 0, chr_bank|data ); } else { SetVROM_1K_Bank( 0, chr_bank|data ); } break; case 0x8311: if( patch ) { SetVROM_2K_Bank( 2, chr_bank|data ); } else { SetVROM_1K_Bank( 1, chr_bank|data ); } break; case 0x8312: SetVROM_1K_Bank( 2, chr_bank|data ); break; case 0x8313: SetVROM_1K_Bank( 3, chr_bank|data ); break; case 0x8314: SetVROM_1K_Bank( 4, chr_bank|data ); break; case 0x8315: SetVROM_1K_Bank( 5, chr_bank|data ); break; case 0x8316: if( patch ) { SetVROM_2K_Bank( 4, chr_bank|data ); } else { SetVROM_1K_Bank( 6, chr_bank|data ); } break; case 0x8317: if( patch ) { SetVROM_2K_Bank( 6, chr_bank|data ); } else { SetVROM_1K_Bank( 7, chr_bank|data ); } break; case 0x8318: SetPROM_16K_Bank( 4, (reg[0]&0x30)|data ); break; } }
void Mapper019::Write( WORD addr, BYTE data ) { //if( addr >= 0xC000 ) { //DEBUGOUT( "W %04X %02X L:%3d\n", addr, data, nes->GetScanline() ); //} switch( addr & 0xF800 ) { case 0x8000: if( (data < 0xE0) || (reg[0] != 0) ) { SetVROM_1K_Bank( 0, data ); } else { SetCRAM_1K_Bank( 0, data&0x1F ); } break; case 0x8800: if( (data < 0xE0) || (reg[0] != 0) ) { SetVROM_1K_Bank( 1, data ); } else { SetCRAM_1K_Bank( 1, data&0x1F ); } break; case 0x9000: if( (data < 0xE0) || (reg[0] != 0) ) { SetVROM_1K_Bank( 2, data ); } else { SetCRAM_1K_Bank( 2, data&0x1F ); } break; case 0x9800: if( (data < 0xE0) || (reg[0] != 0) ) { SetVROM_1K_Bank( 3, data ); } else { SetCRAM_1K_Bank( 3, data&0x1F ); } break; case 0xA000: if( (data < 0xE0) || (reg[1] != 0) ) { SetVROM_1K_Bank( 4, data ); } else { SetCRAM_1K_Bank( 4, data&0x1F ); } break; case 0xA800: if( (data < 0xE0) || (reg[1] != 0) ) { SetVROM_1K_Bank( 5, data ); } else { SetCRAM_1K_Bank( 5, data&0x1F ); } break; case 0xB000: if( (data < 0xE0) || (reg[1] != 0) ) { SetVROM_1K_Bank( 6, data ); } else { SetCRAM_1K_Bank( 6, data&0x1F ); } break; case 0xB800: if( (data < 0xE0) || (reg[1] != 0) ) { SetVROM_1K_Bank( 7, data ); } else { SetCRAM_1K_Bank( 7, data&0x1F ); } break; case 0xC000: if( !patch ) { if( data <= 0xDF ) { SetVROM_1K_Bank( 8, data ); } else { SetVRAM_1K_Bank( 8, data & 0x01 ); } } break; case 0xC800: if( !patch ) { if( data <= 0xDF ) { SetVROM_1K_Bank( 9, data ); } else { SetVRAM_1K_Bank( 9, data & 0x01 ); } } break; case 0xD000: if( !patch ) { if( data <= 0xDF ) { SetVROM_1K_Bank( 10, data ); } else { SetVRAM_1K_Bank( 10, data & 0x01 ); } } break; case 0xD800: if( !patch ) { if( data <= 0xDF ) { SetVROM_1K_Bank( 11, data ); } else { SetVRAM_1K_Bank( 11, data & 0x01 ); } } break; case 0xE000: SetPROM_8K_Bank( 4, data & 0x3F ); if( patch == 2 ) { if( data & 0x40 ) SetVRAM_Mirror( VRAM_VMIRROR ); else SetVRAM_Mirror( VRAM_MIRROR4L ); } if( patch == 3 ) { if( data & 0x80 ) SetVRAM_Mirror( VRAM_HMIRROR ); else SetVRAM_Mirror( VRAM_VMIRROR ); } break; case 0xE800: reg[0] = data & 0x40; reg[1] = data & 0x80; SetPROM_8K_Bank( 5, data & 0x3F ); break; case 0xF000: SetPROM_8K_Bank( 6, data & 0x3F ); break; case 0xF800: if( addr == 0xF800 ) { if( exsound_enable ) { nes->apu->ExWrite( addr, data ); } reg[2] = data; } break; } }
void Mapper025::Write( WORD addr, BYTE data ) { //if( addr >= 0xF000 ) //DEBUGOUT( "M25 WR $%04X=$%02X L=%3d\n", addr, data, nes->GetScanline() ); switch( addr & 0xF000 ) { case 0x8000: if(reg[10] & 0x02) { reg[9] = data; SetPROM_8K_Bank( 6, data ); } else { reg[8] = data; SetPROM_8K_Bank( 4, data ); } break; case 0xA000: SetPROM_8K_Bank( 5, data ); break; } switch( addr & 0xF00F ) { case 0x9000: data &= 0x03; if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR ); else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR ); else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L ); else SetVRAM_Mirror( VRAM_MIRROR4H ); break; case 0x9001: case 0x9004: if((reg[10] & 0x02) != (data & 0x02)) { BYTE swap = reg[8]; reg[8] = reg[9]; reg[9] = swap; SetPROM_8K_Bank( 4, reg[8] ); SetPROM_8K_Bank( 6, reg[9] ); } reg[10] = data; break; case 0xB000: reg[0] = (reg[0] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 0, reg[0] ); break; case 0xB002: case 0xB008: reg[0] = (reg[0] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 0, reg[0] ); break; case 0xB001: case 0xB004: reg[1] = (reg[1] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 1, reg[1] ); break; case 0xB003: case 0xB00C: reg[1] = (reg[1] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 1, reg[1] ); break; case 0xC000: reg[2] = (reg[2] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 2, reg[2] ); break; case 0xC002: case 0xC008: reg[2] = (reg[2] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 2, reg[2] ); break; case 0xC001: case 0xC004: reg[3] = (reg[3] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 3, reg[3] ); break; case 0xC003: case 0xC00C: reg[3] = (reg[3] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 3, reg[3] ); break; case 0xD000: reg[4] = (reg[4] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 4, reg[4] ); break; case 0xD002: case 0xD008: reg[4] = (reg[4] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 4, reg[4] ); break; case 0xD001: case 0xD004: reg[5] = (reg[5] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 5, reg[5] ); break; case 0xD003: case 0xD00C: reg[5] = (reg[5] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 5, reg[5] ); break; case 0xE000: reg[6] = (reg[6] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 6, reg[6] ); break; case 0xE002: case 0xE008: reg[6] = (reg[6] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 6, reg[6] ); break; case 0xE001: case 0xE004: reg[7] = (reg[7] & 0xF0) | (data & 0x0F); SetVROM_1K_Bank( 7, reg[7] ); break; case 0xE003: case 0xE00C: reg[7] = (reg[7] & 0x0F) | ((data & 0x0F) << 4); SetVROM_1K_Bank( 7, reg[7] ); break; case 0xF000: irq_latch = (irq_latch & 0xF0) | (data & 0x0F); nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xF002: case 0xF008: irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4); nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xF001: case 0xF004: irq_enable = data & 0x03; // irq_counter = 0x100 - irq_latch; irq_counter = irq_latch; irq_clock = 0; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xF003: case 0xF00C: irq_enable = (irq_enable & 0x01)*3; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; } }
void Mapper027::Write( WORD addr, BYTE data ) { switch( addr & 0xF0CF ) { case 0x8000: if(reg[8] & 0x02) { SetPROM_8K_Bank( 6, data ); } else { SetPROM_8K_Bank( 4, data ); } break; case 0xA000: SetPROM_8K_Bank( 5, data ); break; case 0x9000: data &= 0x03; if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR ); else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR ); else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L ); else SetVRAM_Mirror( VRAM_MIRROR4H ); break; case 0x9002: case 0x9080: reg[8] = data; break; case 0xB000: reg[0] = (reg[0] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 0, reg[0] ); break; case 0xB001: reg[0] = (reg[0] & 0x0F) | (data<< 4); SetVROM_1K_Bank( 0, reg[0] ); break; case 0xB002: reg[1] = (reg[1] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 1, reg[1] ); break; case 0xB003: reg[1] = (reg[1] & 0x0F) | (data<< 4); SetVROM_1K_Bank( 1, reg[1] ); break; case 0xC000: reg[2] = (reg[2] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 2, reg[2] ); break; case 0xC001: reg[2] = (reg[2] & 0x0F) | (data<< 4); SetVROM_1K_Bank( 2, reg[2] ); break; case 0xC002: reg[3] = (reg[3] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 3, reg[3] ); break; case 0xC003: reg[3] = (reg[3] & 0x0F) | (data<< 4); SetVROM_1K_Bank( 3, reg[3] ); break; case 0xD000: reg[4] = (reg[4] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 4, reg[4] ); break; case 0xD001: reg[4] = (reg[4] & 0x0F) | (data<< 4); SetVROM_1K_Bank( 4, reg[4] ); break; case 0xD002: reg[5] = (reg[5] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 5, reg[5] ); break; case 0xD003: reg[5] = (reg[5] & 0x0F) | (data << 4); SetVROM_1K_Bank( 5, reg[5] ); break; case 0xE000: reg[6] = (reg[6] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 6, reg[6] ); break; case 0xE001: reg[6] = (reg[6] & 0x0F) | (data << 4); SetVROM_1K_Bank( 6, reg[6] ); break; case 0xE002: reg[7] = (reg[7] & 0xFF0) | (data & 0x0F); SetVROM_1K_Bank( 7, reg[7] ); break; case 0xE003: reg[7] = (reg[7] & 0x0F) | (data<< 4); SetVROM_1K_Bank( 7, reg[7] ); break; case 0xF000: irq_latch = (irq_latch & 0xF0) | (data & 0x0F); nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xF001: irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4); nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xF003: irq_enable = (irq_enable & 0x01) * 3; irq_clock = 0; nes->cpu->ClrIRQ( IRQ_MAPPER ); break; case 0xF002: irq_enable = data & 0x03; if( irq_enable & 0x02 ) { irq_counter = irq_latch; irq_clock = 0; } nes->cpu->ClrIRQ( IRQ_MAPPER ); break; } }