int main(void) {
char buff[100];
/* Init system clock for maximum system speed */
TM_RCC_InitSystem();
/* Init HAL layer */
HAL_Init();
/* Init leds */
TM_DISCO_LedInit();
/* Init LCD */
TM_LCD_Init();
/* Display fixes */
#if defined(STM32F7_DISCOVERY)
TM_LCD_SetFont(&TM_Font_7x10);
#elif defined(STM32F429_DISCOVERY)
TM_LCD_SetFont(&TM_Font_7x10);
TM_LCD_SetOrientation(3);
#endif
/* Format unique ID */
sprintf(buff, "Unique ID: 0x%08X 0x%08X 0x%08X", TM_ID_GetUnique32(0), TM_ID_GetUnique32(1), TM_ID_GetUnique32(2));
TM_LCD_SetXY(10, 10);
TM_LCD_Puts(buff);
/* Format device signature */
sprintf(buff, "Device signature: 0x%04X", TM_ID_GetSignature());
TM_LCD_SetXY(10, 30);
TM_LCD_Puts(buff);
/* Format revision */
sprintf(buff, "Revision: 0x%04X", TM_ID_GetRevision());
TM_LCD_SetXY(10, 50);
TM_LCD_Puts(buff);
/* Format package */
sprintf(buff, "Package: 0x%04X", TM_ID_GetPackage());
TM_LCD_SetXY(10, 70);
TM_LCD_Puts(buff);
/* Format flash size */
sprintf(buff, "Flash size: %04d kBytes", TM_ID_GetFlashSize());
TM_LCD_SetXY(10, 90);
TM_LCD_Puts(buff);
while (1) {
}
}
int main(void)
{
// Check that you flashed to the correct microcontroller
uint32_t chipId1 = TM_ID_GetUnique32(0);
uint32_t chipId2 = TM_ID_GetUnique32(1);
uint32_t chipId3 = TM_ID_GetUnique32(2);
if(chipId1 != 0x00290044 || chipId2 != 0x30345117 || chipId3 != 0x37333838){
while(1);
}
// Configure the system clock.
// The system clock is 168Mhz.
RCC_HSEConfig(RCC_HSE_ON); // ENABLE HSE (HSE = 8Mhz)
while(!RCC_WaitForHSEStartUp()); // Wait for HSE to stabilize
SystemCoreClockUpdate();
RCC_PCLK1Config(RCC_HCLK_Div4); // Set APB1=42Mhz (168/4)
// Initialize peripheral modules
InitGPIO();
InitNVIC();
InitPedalIntegrity();
InitADC();
InitCAN();
// MCO_Config(); // Clock output
/* Main code */
while(1)
{
Delay(0xFF);
/*
if(CAN_GetITStatus(CAN1,CAN_IT_FMP0) == SET){
CAN_Receive(CAN1,CAN_FIFO0,&msgRx);
if(msgRx.StdId == 0x1){
GPIOC->ODR |= GPIO_Pin_6;
}
}
*/
}
}
/**
* In this function, the hardware should be initialized.
* Called from ethernetif_init().
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void low_level_init(struct netif *netif)
{
#ifdef CHECKSUM_BY_HARDWARE
int i;
#endif
/* set MAC hardware address length */
netif->hwaddr_len = ETHARP_HWADDR_LEN;
/* set MAC hardware address */
#if defined(MAC_ADDR0) && defined(MAC_ADDR1) && defined(MAC_ADDR2) && defined(MAC_ADDR3) && defined(MAC_ADDR4) && defined(MAC_ADDR5)
netif->hwaddr[0] = MAC_ADDR0;
netif->hwaddr[1] = MAC_ADDR1;
netif->hwaddr[2] = MAC_ADDR2;
netif->hwaddr[3] = MAC_ADDR3;
netif->hwaddr[4] = MAC_ADDR4;
netif->hwaddr[5] = MAC_ADDR5;
#warning "User defined MAC is used for MAC address settings. Address is defined as in main.h file"
#endif
#if !defined(MAC_ADDR0) || !defined(MAC_ADDR1) || !defined(MAC_ADDR2) || !defined(MAC_ADDR3) || !defined(MAC_ADDR4) || !defined(MAC_ADDR5)
netif->hwaddr[0] = TM_ID_GetUnique8(0);
netif->hwaddr[1] = TM_ID_GetUnique8(1);
netif->hwaddr[2] = TM_ID_GetUnique8(2);
netif->hwaddr[3] = TM_ID_GetUnique8(3);
netif->hwaddr[4] = TM_ID_GetUnique8(4);
netif->hwaddr[5] = TM_ID_GetUnique8(5);
#warning "Custom MAC address not defined in main.h file. Using unique STM32F4 ID as MAC address"
#endif
/* define below may not be needed because we can set mac based on unique ID written in STM32F4 processor */
#ifdef CUSTOM_MAC
// TODO: add checking for correct mac set, if no custom mac is set use default mac set in main.h
TM_BKPSRAM_Init();
netif->hwaddr[0] = TM_BKPSRAM_Read8(1);
netif->hwaddr[1] = TM_BKPSRAM_Read8(2);
netif->hwaddr[2] = TM_BKPSRAM_Read8(3);
netif->hwaddr[3] = TM_ID_GetUnique32(0);
netif->hwaddr[4] = TM_ID_GetUnique32(1);
netif->hwaddr[5] = TM_ID_GetUnique32(2);
#endif
/* initialize MAC address in ethernet MAC */
ETH_MACAddressConfig(ETH_MAC_Address0, netif->hwaddr);
/* maximum transfer unit */
netif->mtu = 1500;
/* device capabilities */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
/* Initialize Tx Descriptors list: Chain Mode */
ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
/* Initialize Rx Descriptors list: Chain Mode */
ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
#ifdef CHECKSUM_BY_HARDWARE
/* Enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
for(i=0; i<ETH_TXBUFNB; i++)
{
ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
}
#endif
/* Note: TCP, UDP, ICMP checksum checking for received frame are enabled in DMA config */
/* Enable MAC and DMA transmission and reception */
ETH_Start();
}
