mad_status DIGENTRY MIRegistersHost( mad_registers *mr )
{
#if !defined( __BIG_ENDIAN__ )
unsigned_32 temp;
int i;
// Currently harcoded for big endian targets - should be dynamic
// And we really ought to have a 64-bit byte swap routine...
// Convert GPRs
for( i = 0; i < 32; i++ ) {
CONV_BE_32( TRANS_GPREG_LO( mr->ppc, i ) );
CONV_BE_32( TRANS_GPREG_HI( mr->ppc, i ) );
temp = TRANS_GPREG_LO( mr->ppc, i );
TRANS_GPREG_LO( mr->ppc, i ) = TRANS_GPREG_HI( mr->ppc, i );
TRANS_GPREG_HI( mr->ppc, i ) = temp;
}
// Convert FPRs
for( i = 0; i < 32; i++ ) {
CONV_BE_32( TRANS_FPREG_LO( mr->ppc, i ) );
CONV_BE_32( TRANS_FPREG_HI( mr->ppc, i ) );
temp = TRANS_FPREG_LO( mr->ppc, i );
TRANS_FPREG_LO( mr->ppc, i ) = TRANS_FPREG_HI( mr->ppc, i );
TRANS_FPREG_HI( mr->ppc, i ) = temp;
}
// Convert special registers
CONV_BE_32( mr->ppc.iar.u._32[I64LO32] );
CONV_BE_32( mr->ppc.iar.u._32[I64HI32] );
temp = mr->ppc.iar.u._32[I64LO32];
mr->ppc.iar.u._32[I64LO32] = mr->ppc.iar.u._32[I64HI32];
mr->ppc.iar.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.msr.u._32[I64LO32] );
CONV_BE_32( mr->ppc.msr.u._32[I64HI32] );
temp = mr->ppc.msr.u._32[I64LO32];
mr->ppc.msr.u._32[I64LO32] = mr->ppc.msr.u._32[I64HI32];
mr->ppc.msr.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.ctr.u._32[I64LO32] );
CONV_BE_32( mr->ppc.ctr.u._32[I64HI32] );
temp = mr->ppc.ctr.u._32[I64LO32];
mr->ppc.ctr.u._32[I64LO32] = mr->ppc.ctr.u._32[I64HI32];
mr->ppc.ctr.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.lr.u._32[I64LO32] );
CONV_BE_32( mr->ppc.lr.u._32[I64HI32] );
temp = mr->ppc.lr.u._32[I64LO32];
mr->ppc.lr.u._32[I64LO32] = mr->ppc.lr.u._32[I64HI32];
mr->ppc.lr.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.xer );
CONV_BE_32( mr->ppc.cr );
CONV_BE_32( mr->ppc.fpscr );
#endif
return( MS_OK );
}
mad_status DIGENTRY MIRegistersTarget( mad_registers *mr )
{
#if !defined( __BIG_ENDIAN__ )
unsigned_32 temp;
int i;
// Convert GPRs
for( i = 0; i < 32; i++ ) {
CONV_BE_32( TRANS_GPREG_LO( mr->ppc, i ) );
CONV_BE_32( TRANS_GPREG_HI( mr->ppc, i ) );
temp = TRANS_GPREG_LO( mr->ppc, i );
TRANS_GPREG_LO( mr->ppc, i ) = TRANS_GPREG_HI( mr->ppc, i );
TRANS_GPREG_HI( mr->ppc, i ) = temp;
}
// Convert FPRs
for( i = 0; i < 32; i++ ) {
CONV_BE_32( TRANS_FPREG_LO( mr->ppc, i ) );
CONV_BE_32( TRANS_FPREG_HI( mr->ppc, i ) );
temp = TRANS_FPREG_LO( mr->ppc, i );
TRANS_FPREG_LO( mr->ppc, i ) = TRANS_FPREG_HI( mr->ppc, i );
TRANS_FPREG_HI( mr->ppc, i ) = temp;
}
// Convert special registers
CONV_BE_32( mr->ppc.iar.u._32[I64LO32] );
CONV_BE_32( mr->ppc.iar.u._32[I64HI32] );
temp = mr->ppc.iar.u._32[I64LO32];
mr->ppc.iar.u._32[I64LO32] = mr->ppc.iar.u._32[I64HI32];
mr->ppc.iar.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.msr.u._32[I64LO32] );
CONV_BE_32( mr->ppc.msr.u._32[I64HI32] );
temp = mr->ppc.msr.u._32[I64LO32];
mr->ppc.msr.u._32[I64LO32] = mr->ppc.msr.u._32[I64HI32];
mr->ppc.msr.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.ctr.u._32[I64LO32] );
CONV_BE_32( mr->ppc.ctr.u._32[I64HI32] );
temp = mr->ppc.ctr.u._32[I64LO32];
mr->ppc.ctr.u._32[I64LO32] = mr->ppc.ctr.u._32[I64HI32];
mr->ppc.ctr.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.lr.u._32[I64LO32] );
CONV_BE_32( mr->ppc.lr.u._32[I64HI32] );
temp = mr->ppc.lr.u._32[I64LO32];
mr->ppc.lr.u._32[I64LO32] = mr->ppc.lr.u._32[I64HI32];
mr->ppc.lr.u._32[I64HI32] = temp;
CONV_BE_32( mr->ppc.xer );
CONV_BE_32( mr->ppc.cr );
CONV_BE_32( mr->ppc.fpscr );
#endif
return( MS_OK );
}
static void WriteCPU( struct mips_mad_registers *r )
{
int i;
/* Write special registers */
ptrace( PTRACE_POKEUSER, pid, (void *)PC, (void *)(r->pc.u._32[I64LO32]) );
ptrace( PTRACE_POKEUSER, pid, (void *)MMLO, (void *)r->lo );
ptrace( PTRACE_POKEUSER, pid, (void *)MMHI, (void *)r->hi );
/* Write GPRs */
for( i = 0; i < 32; ++i ) {
ptrace( PTRACE_POKEUSER, pid, (void *)i, (void *)TRANS_GPREG_32( r, i ) );
}
/* Write FPRs */
for( i = 0; i < 16; ++i ) {
ptrace( PTRACE_POKEUSER, pid, (void *)(FPR_BASE + i * 2), (void *)TRANS_FPREG_LO( r, i ) );
ptrace( PTRACE_POKEUSER, pid, (void *)(FPR_BASE + i * 2 + 1), (void *)TRANS_FPREG_HI( r, i ) );
}
}
static void ReadCPU( struct mips_mad_registers *r )
{
int i;
memset( r, 0, sizeof( *r ) );
/* Read GPRs */
for( i = 0; i < 32; ++i ) {
TRANS_GPREG_32( r, i ) = ptrace( PTRACE_PEEKUSER, pid, (void *)i, NULL );
}
/* Read FPRs */
for( i = 0; i < 16; ++i ) {
TRANS_FPREG_LO( r, i ) = ptrace( PTRACE_PEEKUSER, pid, (void *)(FPR_BASE + i * 2), NULL );
TRANS_FPREG_HI( r, i ) = ptrace( PTRACE_PEEKUSER, pid, (void *)(FPR_BASE + i * 2 + 1), NULL );
}
/* Read special registers */
r->pc.u._32[I64LO32] = ptrace( PTRACE_PEEKUSER, pid, (void *)PC, NULL );
r->lo = ptrace( PTRACE_PEEKUSER, pid, (void *)MMLO, NULL );
r->hi = ptrace( PTRACE_PEEKUSER, pid, (void *)MMHI, NULL );
r->fpcsr = ptrace( PTRACE_PEEKUSER, pid, (void *)FPC_CSR, NULL );
r->fpivr = ptrace( PTRACE_PEEKUSER, pid, (void *)FPC_EIR, NULL );
last_eip = r->pc.u._32[I64LO32];
}
