/**
* \internal
* \brief This test sends a packet from the master, and checks
* that the sending happens without errors. Master is megaRF device and the slave
* is on board EEPROM.Configuring EEPROM as slave is not required.
* \param test Current test case.
*/
static void run_twi_master_send_test(const struct test_case *test)
{
status_code_t master_status;
volatile uint64_t delay=0;
// Package to send
twi_package_t packet = {
.addr[0] = (uint8_t) SLAVE_MEM_ADDR, /* TWI slave memory
* address data */
.addr_length = (uint8_t)SLAVE_MEM_ADDR_LENGTH, /* TWI slave
* memory
* address data
* size */
.chip = TWI_SLAVE_ADDR, /* TWI slave bus address */
.buffer = (void *)test_pattern, /* transfer data source
* buffer */
.length = PATTERN_TEST_LENGTH /* transfer data size
* (bytes) */
};
/* TWI master initialization options. */
twi_master_options_t m_options = {
.speed = TWI_SPEED,
.chip = TWI_SLAVE_ADDR,
};
m_options.baud_reg = TWI_CLOCK_RATE(sysclk_get_cpu_hz(), m_options.speed);
// Initialize TWI_MASTER
sysclk_enable_peripheral_clock(TWI_MASTER);
twi_master_init(TWI_MASTER, &m_options);
// Send package to slave
master_status = twi_master_write(TWI_MASTER, &packet);
/* Write completion time for EEPROM */
for(delay=0;delay<10000;delay++);
test_assert_true(test, master_status == STATUS_OK,
"Master write not ok");
}
/**
* \internal
* \brief This test requests previously sent packet to be sent from the slave,
* and checks that the correct packet is received by the master. Master is
* megaRF device and the slave is on board EEPROM.Configuring EEPROM as slave
* is not required.
* \param test Current test case.
*/
static void run_twi_master_recv_test(const struct test_case *test)
{
uint8_t i = 0;
uint8_t recv_pattern[PATTERN_TEST_LENGTH] = {0};
// Package to send
twi_package_t packet = {
.addr[0] = (uint8_t) SLAVE_MEM_ADDR, /* TWI slave memory
* address data */
.addr_length = (uint8_t)SLAVE_MEM_ADDR_LENGTH, /* TWI slave
* memory
* address data
* size */
.chip = TWI_SLAVE_ADDR,
.buffer = (void *)recv_pattern,
.length = PATTERN_TEST_LENGTH,
};
/* TWI master initialization options. */
twi_master_options_t m_options = {
.speed = TWI_SPEED,
.chip = TWI_SLAVE_ADDR,
};
m_options.baud_reg = TWI_CLOCK_RATE(sysclk_get_cpu_hz(), m_options.speed);
// Initialize TWI_MASTER
sysclk_enable_peripheral_clock(TWI_MASTER);
twi_master_init(TWI_MASTER, &m_options);
// Send package to slave
twi_master_read(TWI_MASTER, &packet);
for (i = 0; i < PATTERN_TEST_LENGTH; i++) {
test_assert_true(test, recv_pattern[i] == test_pattern[i],
"Wrong twi data[%d] received, %d != %d", i,
recv_pattern[i],
test_pattern[i]);
}
}
//@}
/**
* \brief Run TWI unit tests
*
* Initializes the clock system, board and serial output, then sets up the
* TWI unit test suite and runs it.
*/
int main(void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS,
};
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
// Define single ended conversion test cases
DEFINE_TEST_CASE(twi_master_send_test, NULL,
run_twi_master_send_test, NULL,
"Sending packet from master test");
DEFINE_TEST_CASE(twi_master_recv_test, NULL,
run_twi_master_recv_test, NULL,
"Receiving packet from slave test");
// Put test case addresses in an array
DEFINE_TEST_ARRAY(twi_tests) = {
&twi_master_send_test,
&twi_master_recv_test,
};
// Define the test suite
DEFINE_TEST_SUITE(twi_suite, twi_tests,
"MEGARF TWI driver test suite");
// Run all tests in the suite
test_suite_run(&twi_suite);
while (1) {
// Intentionally left empty.
}
}
/** \brief TWI Master Example Main
*
* The master example begins by initializing required board resources. The
* system clock, basic GPIO pin mapping, and interrupt vectors are established.
*
* A memory location on a TWI slave is written with a fixed test pattern which
* is then read back into a separate buffer. As a basic sanity check, the
* original write-buffer values are compared with values read from the slave to
* a separate buffer. An LED on the development board is illuminated when there
* is a match between the written and read data.
*
* \return Nothing.
*/
int main(void)
{
/* Initialize the common clock service, board-specific initialization,
* and
* interrupt vector support prior to using the TWI master interfaces.
*/
sysclk_init();
board_init();
/* TWI master initialization options. */
twi_master_options_t opt = {
.speed = TWI_SPEED_HZ,
.chip = SLAVE_BUS_ADDR,
};
opt .baud_reg = TWI_CLOCK_RATE(sysclk_get_cpu_hz(), opt.speed);
/* Enable the peripheral clock for TWI module */
sysclk_enable_peripheral_clock(TWI_EXAMPLE);
/* Initialize the TWI master driver. */
twi_master_init(TWI_EXAMPLE,&opt);
twi_package_t packet = {
.addr[0] = slave_mem_addr[0], /* TWI slave memory
* address data */
.addr_length = (uint8_t)SLAVE_MEM_ADDR_LENGTH, /* TWI slave
* memory
* address data
* size */
.chip = SLAVE_BUS_ADDR, /* TWI slave bus address */
.buffer = (void *)test_pattern, /* transfer data source
* buffer */
.length = PATTERN_TEST_LENGTH /* transfer data size
* (bytes) */
};
/* Perform a multi-byte write access then check the result. */
while (twi_master_write(TWI_EXAMPLE,&packet) != TWI_SUCCESS) {
}
/* Write completion time for EEPROM */
delay_ms(5);
uint8_t data_received[PATTERN_TEST_LENGTH] = {0};
twi_package_t packet_received = {
.addr[0] = slave_mem_addr[0], /* TWI slave memory
* address data */
.addr_length = (uint8_t)SLAVE_MEM_ADDR_LENGTH, /* TWI slave
* memory
* address data
* size */
.chip = SLAVE_BUS_ADDR, /* TWI slave bus address */
.buffer = data_received, /* transfer data destination
* buffer */
.length = PATTERN_TEST_LENGTH /* transfer data size
* (bytes) */
};
/* Perform a multi-byte read access then check the result. */
while (twi_master_read(TWI_EXAMPLE,&packet_received) != TWI_SUCCESS) {
}
/* Verify that the received data matches the sent data. */
for (int i = 0; i < PATTERN_TEST_LENGTH; i++) {
if (data_received[i] != test_pattern[i]) {
/* Error */
while (1) {
}
}
}
/* test PASS */
/* Green LED ON */
LED_On(LED_GREEN_GPIO);
while (1) {
}
}
