/* spi write a data frame,type mean command or data */ int spi_write_9bit(u32 type, u32 value) { // if(type != 0 && type != 1) // return -1; /*make a data frame of 9 bits,the 8th bit 0:mean command,1:mean data*/ value &= 0xff; value |= type; type = 9; CS_CLR(); //udelay(2); while(type--) { CLK_CLR(); if(value & 0x100) TXD_SET(); else TXD_CLR(); value <<= 1; //udelay(2); CLK_SET(); //udelay(2); } CS_SET(); TXD_SET(); return 0; }
static void spi_send_data(unsigned int data) { unsigned int i; CS_SET(); udelay(1); CLK_SET(); TXD_SET(); CS_CLR(); udelay(1); for (i = 0; i < 24; i++) { //udelay(1); CLK_CLR(); udelay(1); if (data & 0x00800000) { TXD_SET(); } else { TXD_CLR(); } udelay(1); CLK_SET(); udelay(1); data <<= 1; } TXD_SET(); CS_SET(); }
void Spi_Write_data(unsigned char data) { int j; CS_CLR(); TXD_SET(); udelay(UDELAY_TIME); CLK_CLR(); udelay(3); CLK_SET(); udelay(UDELAY_TIME); TXD_CLR(); CLK_CLR(); for(j=0; j<8; j++) { if(data&0x80) { TXD_SET(); } else { TXD_CLR(); } data<<=1; CLK_CLR(); udelay(UDELAY_TIME); CLK_SET(); udelay(UDELAY_TIME); } CS_SET(); }
void spi_screenreg_set(u32 Addr, u32 Data) { u32 i; TXD_OUT(); CLK_OUT(); CS_OUT(); DRVDelayUs(2); DRVDelayUs(2); CS_SET(); TXD_CLR(); CLK_CLR(); DRVDelayUs(2); CS_CLR(); for(i = 0; i < 7; i++) //reg { if(Addr &(1<<(6-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } TXD_CLR(); //write // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); for(i = 0; i < 8; i++) //data { if(Data &(1<<(7-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } CS_SET(); CLK_CLR(); TXD_CLR(); DRVDelayUs(2); }
void spi_screenreg_param(u8 Param) { u32 i; u32 control_bit; CS_CLR(); control_bit = 0x0100; Param = (control_bit | Param); //printk("data0 is 0x%x \n", Data); for(i = 0; i < 9; i++) //data { if(Param &(1<<(8-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_SET(); DRVDelayUs(2); CLK_CLR(); DRVDelayUs(2); } CS_SET(); CLK_CLR(); TXD_CLR(); DRVDelayUs(10); }
void Spi_Write_index(unsigned char index) { int j; CS_CLR(); TXD_CLR(); //0 udelay(UDELAY_TIME); CLK_CLR(); udelay(3);// CLK_SET(); udelay(UDELAY_TIME); TXD_CLR(); CLK_CLR(); for(j=0; j<8; j++) { if(index&0x80) { TXD_SET(); } else { TXD_CLR(); } index<<=1; CLK_CLR(); udelay(UDELAY_TIME); CLK_SET(); udelay(UDELAY_TIME); } CS_SET(); }
void WriteCommand( int Command) { unsigned char i,count1, count2,count3,count4; count1= Command>>8; count2= Command; count3=0x20;//00100000 //写命令高位 count4=0x00;//00000000 //写命令低位======具体请看IC的Datasheet CS_CLR(); for(i=0;i<8;i++) { CLK_CLR(); if (count3 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count3<<=1; } for(i=0;i<8;i++) { CLK_CLR(); if (count1 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count1<<=1; } for(i=0;i<8;i++) { CLK_CLR(); if (count4 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count4<<=1; } for(i=0;i<8;i++) { CLK_CLR(); if (count2 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count2<<=1; } CS_SET(); }
static void spi_recv_data(unsigned int* data) { unsigned int i = 0, temp = 0x73; //read data CS_SET(); udelay(1); CLK_SET(); TXD_SET(); CS_CLR(); udelay(1); for(i = 0; i < 8; i++) // 8 bits Data { udelay(1); CLK_CLR(); if (temp & 0x80) TXD_SET(); else TXD_CLR(); temp <<= 1; udelay(1); CLK_SET(); udelay(1); } udelay(1); temp = 0; for(i = 0; i < 16; i++) // 16 bits Data { udelay(1); CLK_CLR(); udelay(1); CLK_SET(); udelay(1); temp <<= 1; if(RXD_GET() == GPIO_HIGH) temp |= 0x01; } TXD_SET(); CS_SET(); *data = temp; }
void spi_screenreg_cmd(u8 Addr) { u32 i; u32 control_bit; TXD_OUT(); CLK_OUT(); CS_OUT(); DRVDelayUs(2); DRVDelayUs(2); CS_SET(); TXD_SET(); CLK_CLR(); DRVDelayUs(30); CS_CLR(); control_bit = 0x0000; Addr = (control_bit | Addr);//spi_screenreg_set(0x36, 0x0000, 0xffff); //printk("addr is 0x%x \n", Addr); for(i = 0; i < 9; i++) //reg { if(Addr &(1<<(8-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_SET(); DRVDelayUs(2); CLK_CLR(); DRVDelayUs(2); } CS_SET(); TXD_SET(); CLK_CLR(); DRVDelayUs(10); }
void spi_screenreg_set(u32 Addr, u32 Data) { #define DRVDelayUs(i) udelay(i*2) u32 i; TXD_OUT(); CLK_OUT(); CS_OUT(); DRVDelayUs(2); DRVDelayUs(2); CS_SET(); TXD_SET(); CLK_SET(); DRVDelayUs(2); CS_CLR(); for(i = 0; i < 6; i++) //reg { if(Addr &(1<<(5-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } TXD_CLR(); //write // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); TXD_SET(); //highz // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); for(i = 0; i < 8; i++) //data { if(Data &(1<<(7-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } CS_SET(); CLK_CLR(); TXD_CLR(); DRVDelayUs(2); }
void spi_screenreg_set(u32 Addr, u32 Data) { #define DRVDelayUs(i) udelay(i*2) u32 i; u32 control_bit; TXD_OUT(); CLK_OUT(); CS_OUT(); DRVDelayUs(2); DRVDelayUs(2); CS_SET(); TXD_SET(); CLK_SET(); DRVDelayUs(2); CS_CLR(); control_bit = 0x70<<8; Addr = (control_bit | Addr); //printk("addr is 0x%x \n", Addr); for(i = 0; i < 16; i++) //reg { if(Addr &(1<<(15-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } CS_SET(); TXD_SET(); CLK_SET(); DRVDelayUs(2); CS_CLR(); control_bit = 0x72<<8; Data = (control_bit | Data); //printk("data is 0x%x \n", Data); for(i = 0; i < 16; i++) //data { if(Data &(1<<(15-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } CS_SET(); CLK_CLR(); TXD_CLR(); DRVDelayUs(2); }
void spi_screenreg_set(uint32 Addr, uint32 Data) { #define CS_OUT() GPIOSetPinDirection(GPIOPortB_Pin3, GPIO_OUT) #define CS_SET() GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH) #define CS_CLR() GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW) #define CLK_OUT() GPIOSetPinDirection(GPIOPortE_Pin5, GPIO_OUT) //I2C0_SCL #define CLK_SET() GPIOSetPinLevel(GPIOPortE_Pin5, GPIO_HIGH) #define CLK_CLR() GPIOSetPinLevel(GPIOPortE_Pin5, GPIO_LOW) #define TXD_OUT() GPIOSetPinDirection(GPIOPortE_Pin4, GPIO_OUT) //I2C0_SDA #define TXD_SET() GPIOSetPinLevel(GPIOPortE_Pin4, GPIO_HIGH) #define TXD_CLR() GPIOSetPinLevel(GPIOPortE_Pin4, GPIO_LOW) #define DRVDelayUs(i) udelay(i*2) uint32 i; TXD_OUT(); CLK_OUT(); CS_OUT(); DRVDelayUs(2); DRVDelayUs(2); CS_SET(); TXD_CLR(); CLK_CLR(); DRVDelayUs(2); CS_CLR(); for(i = 0; i < 7; i++) //reg { if(Addr &(1<<(6-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } TXD_CLR(); //write // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); for(i = 0; i < 8; i++) //data { if(Data &(1<<(7-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } CS_SET(); CLK_CLR(); TXD_CLR(); DRVDelayUs(2); }
void WriteParameter(char DH) { unsigned char i, count1, count2,count3,count4; count1=DH>>8; count2=DH; count3=0x60;//写数据高位 count4=0x40;//写数据低位 CS_CLR(); /* TXD_CLR(); CLK_CLR(); CLK_SET(); //WRITE TXD_SET(); CLK_CLR(); CLK_SET(); //DATA TXD_SET(); CLK_CLR(); CLK_SET(); //HIGH BYTE TXD_CLR(); CLK_CLR(); CLK_SET(); TXD_CLR(); CLK_CLR(); CLK_SET(); TXD_CLR(); CLK_CLR(); CLK_SET(); TXD_CLR(); CLK_CLR(); CLK_SET(); TXD_CLR(); CLK_CLR(); CLK_SET(); */ /* //因为数据的高位基本是不用的,可以不传高位,直接传低位 for(i=0;i<8;i++) { CLK_CLR(); if (count3 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count3<<=1; } for(i=0;i<8;i++) { CLK_CLR(); if (count1 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count1<<=1; } */ for(i=0;i<8;i++) { CLK_CLR(); if (count4 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count4<<=1; } for(i=0;i<8;i++) { CLK_CLR(); if (count2 & 0x80) TXD_SET(); else TXD_CLR(); CLK_SET(); count2<<=1; } CS_SET(); }
//void spi_screenreg_set(uint32 Addr, uint32 Data) void spi_screenreg_set(u32 Data) { u32 i; TXD_OUT(); CLK_OUT(); CS_OUT(); DRVDelayUs(2); DRVDelayUs(2); CS_SET(); TXD_SET(); CLK_SET(); DRVDelayUs(2); CS_CLR(); for(i = 0; i < 16; i++) //reg { if(Data &(1<<(15-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } /* TXD_CLR(); //write // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); TXD_SET(); //highz // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); //for(i = 0; i < 8; i++) //data for(i = 0; i < 16; i++) { if(Data &(1<<(15-i))) TXD_SET(); else TXD_CLR(); // \u6a21\u62dfCLK CLK_CLR(); DRVDelayUs(2); CLK_SET(); DRVDelayUs(2); } */ CS_SET(); CLK_CLR(); TXD_CLR(); DRVDelayUs(2); }