//----------------------------------------------//
//Sends a NFC command and waits for response. //
//----------------------------------------------//
void
InitiatorRequest(u08_t *pbuf)
{
u08_t command[2];
IRQ_ON;
if(active)
{
if (! NfcRfCollisionAvoidance(0x00))
{
Trf797xReset();
return;
}
}
NfcSend(pbuf);//NFCSendLONG(pbuf);
IRQ_OFF;
Trf797xReset();
Trf797xStopDecoders(); // Reset Decoders
Trf797xRunDecoders();
command[0] = IRQ_STATUS; //IRQ status register address
Trf797xReadSingle(command, 1); //function call for single address read
command[0] = MODULATOR_CONTROL; //analog output
command[1] = MODULATOR_CONTROL;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT3;
Trf797xWriteSingle(command, 2);
if(active)
{
command[0] = CHIP_STATE_CONTROL; //analog output
command[1] = CHIP_STATE_CONTROL;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT1;
Trf797xWriteSingle(command, 2);
}
nfc_state = 0; //save the recieved response after the host bufer
i_reg = 0x01;
IRQ_ON;
while(i_reg == 0x01)
{ //wait for end of RX or timer IRQ
McuCounterSet(); //TimerA set
COUNT_VALUE = 0xCE20; //20ms 0x4E20;
START_COUNTER; //start timer up mode
irq_flag = 0x00;
while(irq_flag == 0x00)
{
}
}//while
IRQ_OFF;
Trf797xStopDecoders();
}//InitiatorRequest
void low_setRF_Protocol_ISO14443A()
{
int init_ms;
uint8_t fifo_size;
uint8_t data_buf[5];
/* Test ISO14443-A/Mifare read UID */
init_ms = Trf797xInitialSettings();
Trf797xReset();
/* Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz)) */
data_buf[0] = MODULATOR_CONTROL;
data_buf[1] = 0x31;
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = MODULATOR_CONTROL;
Trf797xReadSingle(data_buf, 1);
/* Configure Mode ISO Control Register (0x01) to 0x88 (ISO14443A RX bit rate, 106 kbps) and no RX CRC (CRC is not present in the response)) */
data_buf[0] = ISO_CONTROL;
data_buf[1] = 0x88;
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = ISO_CONTROL;
Trf797xReadSingle(data_buf, 1);
if(data_buf[0] != 0x88) {
// hydraNfcLowLevelException.errorCode = 0x02;
// hydraNfcLowLevelException.errorMessage = "low_setRF_Protocol_ISO14443A Error- ISO_CONTROL Error";
// Throw hydraNfcLowLevelException;
}
/* Turn RF ON (Chip Status Control Register (0x00)) */
Trf797xTurnRfOn();
/* Read back (Chip Status Control Register (0x00) shall be set to RF ON */
data_buf[0] = CHIP_STATE_CONTROL;
Trf797xReadSingle(data_buf, 1);
return (uint32_t)data_buf[0];
}
void show_registers(t_hydra_console *con)
{
unsigned int i;
static uint8_t data_buf;
memset(buf, 0x20, 30);
buf[30] = 0;
cprintf(con, "TRF7970A Registers:\r\n");
for (i = 0; i < ARRAY_SIZE(registers); i++) {
data_buf = registers[i].reg;
if (data_buf == IRQ_STATUS)
Trf797xReadIrqStatus(&data_buf);
else
Trf797xReadSingle(&data_buf, 1);
cprintf(con, "0x%02x\t%s%s: 0x%02x\r\n", registers[i].reg,
registers[i].name, buf + strlen(registers[i].name),
data_buf);
}
}
static bool hydranfc_test_shield(void)
{
int init_ms;
int err;
static uint8_t data_buf[4];
err = 0;
/* Software Init TRF7970A */
init_ms = Trf797xInitialSettings();
if (init_ms == TRF7970A_INIT_TIMEOUT)
return FALSE;
Trf797xReset();
data_buf[0] = CHIP_STATE_CONTROL;
Trf797xReadSingle(data_buf, 1);
if (data_buf[0] != 0x01)
err++;
return err == 0;
}
void hydranfc_tag_emul_init(void)
{
uint8_t data_buf[4];
Trf797xInitialSettings();
Trf797xReset();
/* ISO Control */
data_buf[0] = ISO_CONTROL;
data_buf[1] = 0x24; /* ISO14443A */
Trf797xWriteSingle(data_buf, 2);
/* Configure RX */
data_buf[0] = RX_SPECIAL_SETTINGS;
data_buf[1] = 0x3C;
Trf797xWriteSingle(data_buf, 2);
/* Configure Adjustable FIFO IRQ Levels Register (96B RX & 32B TX) */
data_buf[0] = 0x14;
data_buf[1] = 0x0F;
Trf797xWriteSingle(data_buf, 2);
/* Configure NFC Target Detection Level Register */
/* RF field level required for system wakeup to max */
data_buf[0] = NFC_TARGET_LEVEL;
data_buf[1] = NFC_TARGET_LEVEL;
data_buf[2] = 0x16; // NFC_LOW_DETECTION
data_buf[3] = BIT0;
// read the NFCTargetLevel register
Trf797xReadSingle(&data_buf[1], 1);
data_buf[1] |= BIT2 + BIT1 + BIT0;
switch(tag_uid_len) {
case 4:
data_buf[1] &= ~(BIT7 + BIT6);
break;
case 7:
data_buf[1] &= ~BIT7;
data_buf[1] |= BIT6;
break;
case 10:
data_buf[1] &= ~BIT6;
data_buf[1] |= BIT7;
break;
default:
break;
}
data_buf[1] |= BIT5; /* SDD Enabled */
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = ISO_14443B_OPTIONS;
data_buf[1] = ISO_14443B_OPTIONS;
Trf797xReadSingle(&data_buf[1], 1);
data_buf[1] |= BIT0; // set 14443A - 4 compliant bit
data_buf[2] = CHIP_STATE_CONTROL;
data_buf[3] = 0x21;
Trf797xWriteSingle(data_buf, 4);
/* Configure Test Register */
/* MOD Pin becomes receiver digitized subcarrier output */
/*
data_buf[0] = TEST_SETTINGS_1;
data_buf[1] = 0x40;
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = MODULATOR_CONTROL;
data_buf[1] = MODULATOR_CONTROL;
Trf797xReadSingle(&data_buf[1], 1);
data_buf[1] |= BIT3;
Trf797xWriteSingle(data_buf, 2);
*/
write_emul_tag_uid(tag_uid);
Trf797xResetIrqStatus();
Trf797xReset();
Trf797xStopDecoders();
Trf797xRunDecoders();
}
void TagIRQ(int irq_status)
{
uint8_t data_buf[32];
int fifo_size;
// RF collision avoidance error
if( (irq_status & BIT0) == BIT0) {
hydranfc_tag_emul_init();
return;
}
/* RF field level */
if( (irq_status & BIT2) == BIT2) {
// printf_dbg("RF\r\n");
}
/* SDD OK */
if( (irq_status & BIT3) == BIT3) {
Tag14443A();
// printf_dbg("SDD OK\r\n");
}
/* Communication error */
if( (irq_status & BIT4) == BIT4) {
hydranfc_tag_emul_init();
return;
/*
data_buf[0] = RX_SPECIAL_SETTINGS; //check filter and gain
Trf797xReadSingle(data_buf, 1);
Trf797xStopDecoders();
return;
*/
}
/* RX */
if( (irq_status & BIT6) == BIT6) {
data_buf[0] = FIFO_CONTROL;
Trf797xReadSingle(data_buf, 1); // determine the number of bytes left in FIFO
fifo_size = data_buf[0] & 0x7F; /* Clear Flag FIFO Overflow */
fifo_size = fifo_size & 0x1F; /* Limit Fifo size to 31bytes */
/* Receive data from FIFO */
if(fifo_size > 0) {
data_buf[0] = FIFO;
Trf797xReadCont(data_buf, fifo_size);
/*
printf_dbg("RX: ");
for(i=0; i<fifo_size; i++) {
printf_dbg("0x%02X ", data_buf[i]);
}
printf_dbg("\r\n");
*/
Trf797xReset(); //reset the FIFO after last byte has been read out
Trf797xResetIrqStatus();
/* Reply ATS (DESFire EV1) */
/*
data_buf[0] = 0x06;
data_buf[1] = 0x75;
data_buf[2] = 0x81;
data_buf[3] = 0x02;
data_buf[4] = 0x80;
if(emul_14443a_tx_rawdata(data_buf, 5, 0) == 5) {
error=0;
} else
error=1;
*/
}
hydranfc_tag_emul_init();
return;
}
/* TX complete */
if( (irq_status & BIT7) == BIT7) {
Trf797xReset(); // reset the FIFO
}
}
void hydranfc_scan_vicinity(t_hydra_console *con)
{
static uint8_t data_buf[VICINITY_UID_MAX];
uint8_t fifo_size;
int i;
/* End Test delay */
irq_count = 0;
/* Test ISO15693 read UID */
Trf797xInitialSettings();
Trf797xReset();
/* Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz)) */
data_buf[0] = MODULATOR_CONTROL;
data_buf[1] = 0x31;
Trf797xWriteSingle(data_buf, 2);
/* Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4) */
data_buf[0] = ISO_CONTROL;
data_buf[1] = 0x02;
Trf797xWriteSingle(data_buf, 2);
/* Configure Test Settings 1 to BIT6/0x40 => MOD Pin becomes receiver subcarrier output (Digital Output for RX/TX) */
/*
data_buf[0] = TEST_SETTINGS_1;
data_buf[1] = BIT6;
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = TEST_SETTINGS_1;
Trf797xReadSingle(data_buf, 1);
if (data_buf[0] != 0x40)
{
cprintf(con, "Error Test Settings Register(0x1A) read=0x%02lX (shall be 0x40)\r\n", (uint32_t)data_buf[0]);
err++;
}
*/
/* Turn RF ON (Chip Status Control Register (0x00)) */
Trf797xTurnRfOn();
McuDelayMillisecond(10);
/* Send Inventory(3B) and receive data + UID */
data_buf[0] = 0x26; /* Request Flags */
data_buf[1] = 0x01; /* Inventory Command */
data_buf[2] = 0x00; /* Mask */
fifo_size = Trf797x_transceive_bytes(data_buf, 3, data_buf, VICINITY_UID_MAX,
10, /* 10ms TX/RX Timeout (shall be less than 10ms (6ms) in High Speed) */
1); /* CRC enabled */
if (fifo_size > 0) {
/* fifo_size should be 10. */
cprintf(con, "UID:");
for (i = 0; i < fifo_size; i++)
cprintf(con, " 0x%02lX", (uint32_t)data_buf[i]);
cprintf(con, "\r\n");
/* Read RSSI levels and oscillator status(0x0F/0x4F) */
data_buf[0] = RSSI_LEVELS;
Trf797xReadSingle(data_buf, 1);
if (data_buf[0] < 0x40) {
cprintf(con, "RSSI error: 0x%02lX (should be > 0x40)\r\n", (uint32_t)data_buf[0]);
}
}
/* Turn RF OFF (Chip Status Control Register (0x00)) */
Trf797xTurnRfOff();
/*
cprintf(con, "irq_count: 0x%02ld\r\n", (uint32_t)irq_count);
irq_count = 0;
*/
}
void hydranfc_scan_mifare(t_hydra_console *con)
{
uint8_t data_buf[MIFARE_DATA_MAX];
uint8_t atqa_buf[MIFARE_ATQA_MAX];
uint8_t uid_buf[MIFARE_UID_MAX];
uint8_t sak1_buf[MIFARE_SAK_MAX];
uint8_t sak2_buf[MIFARE_SAK_MAX];
uint8_t CL1_buf[MIFARE_CL1_MAX];
uint8_t CL2_buf[MIFARE_CL2_MAX];
uint8_t halt_buf[MIFARE_HALT_MAX];
uint8_t atqa_buf_size = 0;
uint8_t uid_buf_size = 0;
uint8_t sak1_buf_size = 0;
uint8_t sak2_buf_size = 0;
uint8_t CL1_buf_size = 0;
uint8_t CL2_buf_size = 0;
uint8_t halt_buf_size = 0;
uint8_t bcc, i;
/* End Test delay */
irq_count = 0;
/* Test ISO14443-A/Mifare read UID */
Trf797xInitialSettings();
Trf797xReset();
/*
* Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK
* and default Clock 13.56Mhz))
*/
data_buf[0] = MODULATOR_CONTROL;
data_buf[1] = 0x31;
Trf797xWriteSingle(data_buf, 2);
/*
* Configure Mode ISO Control Register (0x01) to 0x88 (ISO14443A RX bit
* rate, 106 kbps) and no RX CRC (CRC is not present in the response))
*/
data_buf[0] = ISO_CONTROL;
data_buf[1] = 0x88;
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = ISO_CONTROL;
Trf797xReadSingle(data_buf, 1);
if (data_buf[0] != 0x88)
cprintf(con, "Error ISO Control Register read=0x%02lX (should be 0x88)\r\n",
(uint32_t)data_buf[0]);
/* Configure Test Settings 1 to BIT6/0x40 => MOD Pin becomes receiver subcarrier output (Digital Output for RX/TX) */
/*
data_buf[0] = TEST_SETTINGS_1;
data_buf[1] = BIT6;
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = TEST_SETTINGS_1;
Trf797xReadSingle(data_buf, 1);
if (data_buf[0] != 0x40)
{
cprintf(con, "Error Test Settings Register(0x1A) read=0x%02lX (shall be 0x40)\r\n", (uint32_t)data_buf[0]);
err++;
}
*/
/* Turn RF ON (Chip Status Control Register (0x00)) */
Trf797xTurnRfOn();
/* Send REQA (7 bits) and receive ATQA (2 bytes) */
data_buf[0] = 0x26; /* REQA (7bits) */
atqa_buf_size = Trf797x_transceive_bits(data_buf[0], 7, atqa_buf, MIFARE_ATQA_MAX,
10, /* 10ms TX/RX Timeout */
0); /* TX CRC disabled */
/* Re-send REQA */
if (atqa_buf_size == 0) {
/* Send REQA (7 bits) and receive ATQA (2 bytes) */
data_buf[0] = 0x26; /* REQA (7 bits) */
atqa_buf_size = Trf797x_transceive_bits(data_buf[0], 7, atqa_buf, MIFARE_ATQA_MAX,
10, /* 10ms TX/RX Timeout */
0); /* TX CRC disabled */
}
if (atqa_buf_size > 0) {
/* Send AntiColl Cascade Level1 (2 bytes) and receive CT+3 UID bytes+BCC (5 bytes) [tag 7 bytes UID] or UID+BCC (5 bytes) [tag 4 bytes UID] */
data_buf[0] = 0x93;
data_buf[1] = 0x20;
CL1_buf_size = Trf797x_transceive_bytes(data_buf, 2, CL1_buf, MIFARE_CL1_MAX,
10, /* 10ms TX/RX Timeout */
0); /* TX CRC disabled */
/*Check tag 7 bytes UID*/
if (CL1_buf[0] == 0x88) {
uid_buf_size = 7;
for (i = 0; i < 3; i++) {
uid_buf[i] = CL1_buf[1 + i];
}
/* Send AntiColl Cascade Level1 (2 bytes)+CT+3 UID bytes+BCC (5 bytes) and receive SAK1 (1 byte) */
data_buf[0] = 0x93;
data_buf[1] = 0x70;
for (i = 0; i < CL1_buf_size; i++) {
data_buf[2 + i] = CL1_buf[i];
}
sak1_buf_size = Trf797x_transceive_bytes(data_buf, (2 + CL1_buf_size), sak1_buf, MIFARE_SAK_MAX,
20, /* 10ms TX/RX Timeout */
1); /* TX CRC disabled */
if (sak1_buf_size > 0) {
/* Send AntiColl Cascade Level2 (2 bytes) and receive 4 UID bytes+BCC (5 bytes)*/
data_buf[0] = 0x95;
data_buf[1] = 0x20;
CL2_buf_size = Trf797x_transceive_bytes(data_buf, 2, CL2_buf, MIFARE_CL2_MAX,
10, /* 10ms TX/RX Timeout */
0); /* TX CRC disabled */
if (CL2_buf_size > 0) {
for (i = 0; i < 4; i++) {
uid_buf[i + 3] = CL2_buf[i];
}
data_buf[0] = RSSI_LEVELS;
Trf797xReadSingle(data_buf, 1);
if (data_buf[0] < 0x40)
cprintf(con, "RSSI error: 0x%02lX (should be > 0x40)\r\n", (uint32_t)data_buf[0]);
/*
* Select RX with CRC_A
* Configure Mode ISO Control Register (0x01) to 0x08
* (ISO14443A RX bit rate, 106 kbps) and RX CRC (CRC
* is present in the response)
*/
data_buf[0] = ISO_CONTROL;
data_buf[1] = 0x08;
Trf797xWriteSingle(data_buf, 2);
/* Send AntiColl Cascade Level2 (2 bytes)+4 UID bytes(4 bytes) and receive SAK2 (1 byte) */
data_buf[0] = 0x95;
data_buf[1] = 0x70;
for (i = 0; i < CL2_buf_size; i++) {
data_buf[2 + i] = CL2_buf[i];
}
sak2_buf_size = Trf797x_transceive_bytes(data_buf, (2 + CL2_buf_size), sak2_buf, MIFARE_SAK_MAX,
20, /* 10ms TX/RX Timeout */
1); /* TX CRC disabled */
if (sak2_buf_size > 0) {
/* Send Halt(2Bytes+CRC) */
data_buf[0] = 0x50;
data_buf[1] = 0x00;
halt_buf_size = Trf797x_transceive_bytes(data_buf, 2, halt_buf, MIFARE_HALT_MAX,
5, /* 5ms TX/RX Timeout => shall not receive answer */
1); /* TX CRC enabled */
}
}
}
}
/*tag 4 bytes UID*/
else {
uid_buf_size = Trf797x_transceive_bytes(data_buf, 2, uid_buf, MIFARE_UID_MAX,
10, /* 10ms TX/RX Timeout */
0); /* TX CRC disabled */
if (uid_buf_size > 0) {
data_buf[0] = RSSI_LEVELS;
Trf797xReadSingle(data_buf, 1);
if (data_buf[0] < 0x40)
cprintf(con, "RSSI error: 0x%02lX (should be > 0x40)\r\n", (uint32_t)data_buf[0]);
/*
* Select RX with CRC_A
* Configure Mode ISO Control Register (0x01) to 0x08
* (ISO14443A RX bit rate, 106 kbps) and RX CRC (CRC
* is present in the response)
*/
data_buf[0] = ISO_CONTROL;
data_buf[1] = 0x08;
Trf797xWriteSingle(data_buf, 2);
/* Finish Select (6 bytes) and receive SAK1 (1 byte) */
data_buf[0] = 0x93;
data_buf[1] = 0x70;
for (i = 0; i < uid_buf_size; i++) {
data_buf[2 + i] = uid_buf[i];
}
sak1_buf_size = Trf797x_transceive_bytes(data_buf, (2 + uid_buf_size), sak1_buf, MIFARE_SAK_MAX,
20, /* 20ms TX/RX Timeout */
1); /* TX CRC enabled */
if (sak1_buf_size > 0) {
/* Send Halt(2Bytes+CRC) */
data_buf[0] = 0x50;
data_buf[1] = 0x00;
halt_buf_size = Trf797x_transceive_bytes(data_buf, 2, halt_buf, MIFARE_HALT_MAX,
5, /* 5ms TX/RX Timeout => shall not receive answer */
1); /* TX CRC enabled */
}
}
}
}
/* Turn RF OFF (Chip Status Control Register (0x00)) */
Trf797xTurnRfOff();
if(atqa_buf_size > 0) {
cprintf(con, "ATQA: ");
for (i = 0; i < atqa_buf_size; i++)
cprintf(con, " %02X", (uint32_t)atqa_buf[i]);
cprintf(con, "\r\n");
}
if(sak1_buf_size > 0) {
cprintf(con, "SAK1: ");
if (sak1_buf_size > 1)
sak1_buf_size = 1;
for (i = 0; i < sak1_buf_size; i++)
cprintf(con, " %02lX", (uint32_t)sak1_buf[i]);
cprintf(con, "\r\n");
}
if(sak2_buf_size > 0) {
cprintf(con, "SAK2: ");
for (i = 0; i < sak2_buf_size; i++)
cprintf(con, " %02lX", (uint32_t)sak2_buf[i]);
cprintf(con, "\r\n");
}
if(uid_buf_size > 0) {
if(uid_buf_size == 7) {
cprintf(con, "UID: ");
for (i = 0; i < uid_buf_size ; i++) {
cprintf(con, " %02lX", (uint32_t)uid_buf[i]);
}
cprintf(con, "\r\n");
} else {
cprintf(con, "UID: ");
bcc = 0;
for (i = 0; i < uid_buf_size - 1; i++) {
cprintf(con, " %02lX", (uint32_t)uid_buf[i]);
bcc ^= uid_buf[i];
}
cprintf(con, " (BCC %02lX %s)\r\n", (uint32_t)uid_buf[i],
bcc == uid_buf[i] ? "ok" : "NOT OK");
}
}
if (halt_buf_size > 0) {
cprintf(con, "HALT: ");
for (i = 0; i < halt_buf_size; i++)
cprintf(con, " %02lX", (uint32_t)data_buf[i]);
cprintf(con, "\r\n");
}
/*
cprintf(con, "irq_count: 0x%02ld\r\n", (uint32_t)irq_count);
irq_count = 0;
*/
}
//----------------------------------------------//
//The NFCActiveMain function calls the other NFC//
//functions for Felica (active) mode. //
//----------------------------------------------//
u08_t
NfcMain(u08_t *pbuf, u08_t tag)
{
u08_t i = 0, command[2];
u08_t code = 0;
#if DBG_NFC
command[0] = TEST_SETTINGS_1; //subcarrier output
command[1] = 0x40;
Trf797xWriteSingle(command, 2);
command[0] = MODULATOR_CONTROL; //analog output
command[1] = MODULATOR_CONTROL;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT3;
Trf797xWriteSingle(command, 2);
#endif
reader_mode = 0xFF;
//rxdataPointer = 0;
//RXlen = 0;
Trf797xResetIrqStatus(); //function call for single address read
IRQ_ON;
/*
if ((*(pbuf + 2) == 0x00) || (*(pbuf + 2) == 0x02) || (*(pbuf + 2) == 0x04) || (*(pbuf + 2) == 0x06) || (*(pbuf + 2) == 0x08) || (*(pbuf + 2) == 0x0A) || (*(pbuf + 2) == 0x16))
{
command[0] = ISOControl;
command[1] = NFCIso;
WriteSingle(command, 2);
}
*/
switch(*(pbuf + 2))
{
case 0x00: //ATR_REQ
//send_cstring("ATR\r\n");
do
{
i++;
if(i > 3)
{
code = 1;
goto EXIT;
}
InitiatorRequest(pbuf);
}while((i_reg != 0xFF) && (buf[1] != 0xD5) && (buf[2] != 0x01));
break;
case 0x02: //WUP_REQ
//send_cstring("WUP\r\n");
do
{
i++;
if(i > 3)
{
code = 1;
goto EXIT;
}
InitiatorRequest(pbuf);
}while((i_reg != 0xFF) && (buf[1] != 0xD5) && (buf[2] != 0x03));
break;
case 0x04: //PSL_REQ
//send_cstring("PSL\r\n");
do
{
i++;
if(i > 3)
{
code = 1;
goto EXIT;
}
InitiatorRequest(pbuf);
}while((i_reg != 0xFF) && (buf[1] != 0xD5) && (buf[2] != 0x05));
break;
case 0x06: //DEP_REQ
//send_cstring("DEP\r\n");
while(!InitiatorDepRequest(pbuf))
{
i++;
if(i > 1)
{
code = 1;
goto EXIT;
}
}//while
break;
case 0x08: //DSL_REQ
//send_cstring("DSL\r\n");
do
{
i++;
if(i > 3)
{
code = 1;
goto EXIT;
}
InitiatorRequest(pbuf);
}while((i_reg != 0xFF) && (buf[1] != 0xD5) && (buf[2] != 0x09));
break;
case 0x0A: //RLS_REQ
//send_cstring("RLS\r\n");
do
{
i++;
if(i > 3)
{
code = 1;
goto EXIT;
}
InitiatorRequest(pbuf);
}while((i_reg != 0xFF) && (buf[1] != 0xD5) && (buf[1] != 0x0B));
break;
case 0x0C: //Select target mode, CID is recieved with the command
//send_cstring("target\r\n");
nfc_iso = ISO_CONTROL;
Trf797xReadSingle(&nfc_iso, 1);
reader_mode = 0xF0; //set for target iterrupt handling
TargetAnticollision(pbuf, tag);
break;
case 0x16: //Data excahange
//kputchar('v');
//kputchar('v');
do
{
i++;
if(i > 1)
{
code = 1;
goto EXIT;
}
//kputchar('x');
//kputchar('x');
InitiatorRequest(pbuf);
//kputchar('w');
//Put_byte(NFCstate);
//kputchar('w');
//Put_byte(i_reg);
//Put_byte(buf[1]);
//Put_byte(buf[2]);
//kputchar('w');
}while((i_reg != 0xFF) && (buf[1] != 0xD5) && (buf[2] != 0x09));
//kputchar('z');
//kputchar('z');
break;
case 0xF0: //select initiator for passive operation
active = 0x00;
//NFCIso = ISOControl;
//ReadSingle(&NFCIso, 1);
#if DBG_NFC
command[0] = TEST_SETTINGS_1; //subcarrier output
command[1] = 0x40;
Trf797xWriteSingle(command, 2);
command[0] = MODULATOR_CONTROL; //analog output
command[1] = MODULATOR_CONTROL;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT3;
Trf797xWriteSingle(command, 2);
#endif
break;
case 0xF1: //select initiator for active operation
active = 0xFF;
//NFCIso = ISOControl;
//ReadSingle(&NFCIso, 1);
//send_cstring("active\r\n");
command[0] = CHIP_STATE_CONTROL;
command[1] = 0x01;
Trf797xWriteSingle(command, 2);
break;
default:
break;
}//switch
IRQ_OFF;
UartSendCString("[00]");
return(code);
EXIT:
IRQ_OFF;
UartSendCString("[]");
return(code);
}//NfcMain
//----------------------------------------------------------------------
//Performs the initial RF collision avoidance. The modulation
//has to be OOK at start and after it completes it has to
//switch to 10-30% AM modulation.
//----------------------------------------------------------------------
u08_t
NfcRfCollisionAvoidance(u08_t mode)
{
u08_t command = 0x00, Register = 0xFF, i = 0x00;
i_reg = 0x01;
Trf797xResetIrqStatus(); //IRQ status register has to be read
while((Register & 0xC0) != 0x00) //Check external RF field.
{
if(i == 0x10) //alow the loop only 15 times
{
return 0;
}
Register = NFC_TARGET_PROTOCOL; //The register 0x19 bit7 and bit6
Trf797xReadSingle(&Register, 1); //If it is below the LOW level
i++; //transmition can begin.
}//while
switch(mode)
{
case 0x00:
command = INITIAL_RF_COLLISION;
break;
case 0x01:
command = RESPONSE_RF_COLLISION_N;
break;
case 0x02:
command = RESPONSE_RF_COLLISION_0;
break;
}//switch
Trf797xDirectCommand(&command); //performs RF collision avoidance
while(i_reg == 0x01) //wait for completition of RF collision avoidance
{
McuCounterSet(); //TimerA set
COUNT_VALUE = 0xF000; //74ms
START_COUNTER; //start timer up mode
irq_flag = 0x00;
while(irq_flag == 0x00)
{
}
/* if(i_reg != 0x01)
break;
CounterSet(); //TimerA set
CountValue = 0xF000; //74ms
startCounter; //start timer up mode
LPM0;
break;
*/
}
switch(i_reg)
{ //If an error occures during RF collision avoidance
case 0x00:
break; //the function terminates.
case 0x02:
return 0;
default:
return 1;
}//switch
/*
if(mode != 0x00){
CounterSet(); //TimerA set
CountValue = 0x352; //1ms
startCounter; //start timer up mode
LPM0;
}*/
return 1;
}//RFCollisionAvoidance
u08_t
NfcFifoSend(u08_t length, u08_t broken_bits, u08_t no_tx_crc, u08_t delayed)
{
#if DBG
u08_t irq_mask[2];
#endif
u08_t code = 0;
IRQ_OFF;
#if DBG
irq_mask[0] = IRQ_MASK;
irq_mask[1] = IRQ_MASK;
Trf797xReadSingle(&irq_mask[1], 1);
irq_mask[1] &= ~BIT2;
Trf797xWriteSingle(irq_mask, 2);
#endif
i_reg = 0x01;
irq_flag = 0x00;
rxtx_state = 12; //RXTXstate global wariable is the main transmit counter
tx_buf[0] = 0x8F;
if(no_tx_crc)
{
tx_buf[1] = 0x90; //buffer setup for FIFO writing
}
else
{
tx_buf[1] = 0x91; //buffer setup for FIFO writing
}
if(delayed)
{
tx_buf[1] |= BIT1; //delayed transmit command
}
tx_buf[2] = 0x3D;
tx_buf[3] = 0x00;
tx_buf[4] = 0xC0 | broken_bits;
//if(lenght > FIFO_LEN)
//lenght = FIFO_LEN;
/*if(length == 0x00 && broken_bits != 0x00)
{
length = 1;
rxtx_state = 1;
}*/
Trf797xRawWrite(tx_buf, (length + 5)); //send the command and data to TRF796x
//Trf797xRawWrite(pbuf, lenght, 0, 1); //send the request using RAW writing
//Write FIFO_LEN bytes the first time you write to FIFO
IRQ_ON;
/*RXTXstate = RXTXstate - FIFO_LEN;
index = FIFO_LEN;
command[0] = 0x3F; //FIFO continous
while(RXTXstate > 0){
CounterSet(); //TimerA set
CountValue = 0x4E20; //20ms
startCounter; //start timer up mode
LPM0;
if(TimerEvent){
code = 1;
goto EXIT;
}
if(RXTXstate > FIFO_MORE){ //the number of unsent bytes is in the RXTXstate global
lenght = FIFO_MORE; //count variable has to be 10 : 9 bytes for FIFO and 1 address
}else if(RXTXstate < 1){
break; //return from interrupt if all bytes have been sent to FIFO
}else{
lenght = RXTXstate; //all data has been sent out
}//if
RAWwrite(command, 1, 1, 0); //write in FIFO address
RAWwrite((pbuf + index), lenght, 0, 1);
RXTXstate = RXTXstate - FIFO_MORE; //write FIFO_MORE bytes to FIFO
index = index + FIFO_MORE;
}//while*/
nfc_state = 1; // the response will be stored in buf[1] upwards
/*if((tx_buf[3] == 0x00) && ((tx_buf[3] >> 4) > 4))
{
irq_flag = 0x00;
McuCounterSet();
COUNT_VALUE = COUNT_60ms; //60ms for TIMEOUT
START_COUNTER; //start timer up mode
while(irq_flag == 0x00)
{
}
}*/
irq_flag = 0x00;
McuCounterSet();
COUNT_VALUE = COUNT_60ms; //60ms for TIMEOUT
START_COUNTER; //start timer up mode
while(i_reg == 0x01) //wait for end of TX interrupt or timeout
{
}
if(irq_flag == 0x03)
{
code = 1;
}
//EXIT:
#if DBG
irq_mask[0] = IRQ_MASK;
irq_mask[1] = IRQ_MASK;
Trf797xReadSingle(&irq_mask[1], 1);
irq_mask[1] |= BIT2;
Trf797xWriteSingle(irq_mask, 2);
#endif
return(code);
} //NfcFifoSend
void
Type2ReadTwoBlocks(u08_t rd2b)
{
u08_t i = 0, command[4];
buf[0] = 0x8F; // reset FIFO
buf[1] = 0x91; // send with CRC
buf[2] = 0x3D; // write continuous from register
buf[3] = 0x00; // value for register 1D
buf[4] = 0x20; // register 1E (# of bytes to be transmitted)
buf[5] = 0x31; // RD2B command
//buf[6+30] = rd2b; // addressed block
buf[200] = 80; // tell apart from Ack/Nack
rx_error_flag = 0x00;
command[0] = SPECIAL_FUNCTION;
command[1] = SPECIAL_FUNCTION;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT2; // enable 4-bit receive
McuCounterSet(); // TimerA set
COUNT_VALUE = COUNT_1ms * 5; // 5ms
IRQ_CLR; // PORT2 interrupt flag clear
IRQ_ON;
Trf797xReset(); // FIFO has to be reset before recieving the next response
Trf797xRawWrite(&buf[0], 7); // set Special Function Register
i_reg = 0x01;
START_COUNTER; // start timer up mode
irq_flag = 0x00;
while(irq_flag == 0x00) // wait for end of TX interrupt
{
}
Trf797xWriteSingle(command, 2); // enable 4-bit receive
rxtx_state = 1; // the response will be stored in buf[1] upwards
McuCounterSet(); // TimerA set
COUNT_VALUE = COUNT_1ms * 10;
START_COUNTER; // start timer up mode
i_reg = 0x01;
while(i_reg == 0x01) // wait for interrupt
{
}
if(rx_error_flag == 0x02)
{
i_reg = 0x02;
}
if(i_reg == 0xFF) // recieved response
{
UartPutChar('[');
for(i = 1; i < rxtx_state; i++)
{
UartPutByte(buf[i]);
}
UartPutChar(']');
}
else if(i_reg == 0x02)
{
if(buf[200] < 0x20) // not acknowledged
{
UartSendCString("[NACK]");
}
else // collision occured
{
UartPutChar('[');
UartPutChar('z');
UartPutChar(']');
}
}
else if(i_reg == 0x00) // no responce
{
UartPutChar('[');
UartPutChar(']');
}
else
{
}
command[0] = SPECIAL_FUNCTION;
command[1] = SPECIAL_FUNCTION;
Trf797xReadSingle(&command[1], 1);
command[1] &= ~BIT2;
Trf797xWriteSingle(command, 2); // disable 4-bit receive
}
void
Type2WriteOneBlock(u08_t wr1b)
{
u08_t command[10];
//for(i=10; i>4; i--) // write parameter in right frameposition
//{
// buf[i+2] = buf[i];
//}
buf[0] = 0x8F; // reset FIFO
buf[1] = 0x91; // send with CRC
buf[2] = 0x3D; // write continuous from register
buf[3] = 0x00; // value for register 1D
buf[4] = 0x60; // register 1E (# of bytes to be transmitted)
buf[5] = 0xA2; // WR2B command
//buf[6] = wr1b;
buf[200] = 80; // tell apart from Ack/Nack
rx_error_flag = 0x00;
command[0] = SPECIAL_FUNCTION;
command[1] = SPECIAL_FUNCTION;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT2;
Trf797xWriteSingle(command, 2); // enable 4-bit receive
Trf797xRawWrite(&buf[0], 11);
IRQ_CLR; // PORT2 interrupt flag clear
IRQ_ON;
i_reg = 0x01;
rxtx_state = 1; // the response will be stored in buf[1] upwards
// wait for end of transmit
while(i_reg == 0x01)
{
McuCounterSet();
COUNT_VALUE = COUNT_1ms * 5; // for 10 ms TIMEOUT
START_COUNTER; // start timer up mode
irq_flag = 0x00;
while(irq_flag == 0x00) // wait for interrupt
{
}
}
i_reg = 0x01;
McuCounterSet(); // TimerA set
COUNT_VALUE = COUNT_1ms * 6; // 6ms
START_COUNTER;
while(i_reg == 0x01) // wait for RX complete
{
}
if(rx_error_flag == 0x02)
{
i_reg = 0x02;
}
if(i_reg == 0x02)
{
if(buf[200] < 0x20) // not acknowledged
{
UartSendCString("[NACK]");
}
else if((buf[200] & 0xF0) == 0xA0) // acknowledged
{
UartSendCString("[ACK]");
}
else // collision occured
{
UartPutChar('[');
UartPutChar('z');
UartPutChar(']');
}
}
else if(i_reg == 0x00) // no response
{
UartPutChar('[');
UartPutChar(']');
}
else
{
}
command[0] = SPECIAL_FUNCTION;
command[1] = SPECIAL_FUNCTION;
Trf797xReadSingle(&command[1], 1);
command[1] &= ~BIT2;
Trf797xWriteSingle(command, 2); // disable 4-bit receive
}
