//----------------------------------------------//
//Sends a NFC command and waits for response. //
//----------------------------------------------//
void
InitiatorRequest(u08_t *pbuf)
{
u08_t command[2];
IRQ_ON;
if(active)
{
if (! NfcRfCollisionAvoidance(0x00))
{
Trf797xReset();
return;
}
}
NfcSend(pbuf);//NFCSendLONG(pbuf);
IRQ_OFF;
Trf797xReset();
Trf797xStopDecoders(); // Reset Decoders
Trf797xRunDecoders();
command[0] = IRQ_STATUS; //IRQ status register address
Trf797xReadSingle(command, 1); //function call for single address read
command[0] = MODULATOR_CONTROL; //analog output
command[1] = MODULATOR_CONTROL;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT3;
Trf797xWriteSingle(command, 2);
if(active)
{
command[0] = CHIP_STATE_CONTROL; //analog output
command[1] = CHIP_STATE_CONTROL;
Trf797xReadSingle(&command[1], 1);
command[1] |= BIT1;
Trf797xWriteSingle(command, 2);
}
nfc_state = 0; //save the recieved response after the host bufer
i_reg = 0x01;
IRQ_ON;
while(i_reg == 0x01)
{ //wait for end of RX or timer IRQ
McuCounterSet(); //TimerA set
COUNT_VALUE = 0xCE20; //20ms 0x4E20;
START_COUNTER; //start timer up mode
irq_flag = 0x00;
while(irq_flag == 0x00)
{
}
}//while
IRQ_OFF;
Trf797xStopDecoders();
}//InitiatorRequest
void hydranfc_tag_emul_init(void)
{
uint8_t data_buf[4];
Trf797xInitialSettings();
Trf797xReset();
/* ISO Control */
data_buf[0] = ISO_CONTROL;
data_buf[1] = 0x24; /* ISO14443A */
Trf797xWriteSingle(data_buf, 2);
/* Configure RX */
data_buf[0] = RX_SPECIAL_SETTINGS;
data_buf[1] = 0x3C;
Trf797xWriteSingle(data_buf, 2);
/* Configure Adjustable FIFO IRQ Levels Register (96B RX & 32B TX) */
data_buf[0] = 0x14;
data_buf[1] = 0x0F;
Trf797xWriteSingle(data_buf, 2);
/* Configure NFC Target Detection Level Register */
/* RF field level required for system wakeup to max */
data_buf[0] = NFC_TARGET_LEVEL;
data_buf[1] = NFC_TARGET_LEVEL;
data_buf[2] = 0x16; // NFC_LOW_DETECTION
data_buf[3] = BIT0;
// read the NFCTargetLevel register
Trf797xReadSingle(&data_buf[1], 1);
data_buf[1] |= BIT2 + BIT1 + BIT0;
switch(tag_uid_len) {
case 4:
data_buf[1] &= ~(BIT7 + BIT6);
break;
case 7:
data_buf[1] &= ~BIT7;
data_buf[1] |= BIT6;
break;
case 10:
data_buf[1] &= ~BIT6;
data_buf[1] |= BIT7;
break;
default:
break;
}
data_buf[1] |= BIT5; /* SDD Enabled */
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = ISO_14443B_OPTIONS;
data_buf[1] = ISO_14443B_OPTIONS;
Trf797xReadSingle(&data_buf[1], 1);
data_buf[1] |= BIT0; // set 14443A - 4 compliant bit
data_buf[2] = CHIP_STATE_CONTROL;
data_buf[3] = 0x21;
Trf797xWriteSingle(data_buf, 4);
/* Configure Test Register */
/* MOD Pin becomes receiver digitized subcarrier output */
/*
data_buf[0] = TEST_SETTINGS_1;
data_buf[1] = 0x40;
Trf797xWriteSingle(data_buf, 2);
data_buf[0] = MODULATOR_CONTROL;
data_buf[1] = MODULATOR_CONTROL;
Trf797xReadSingle(&data_buf[1], 1);
data_buf[1] |= BIT3;
Trf797xWriteSingle(data_buf, 2);
*/
write_emul_tag_uid(tag_uid);
Trf797xResetIrqStatus();
Trf797xReset();
Trf797xStopDecoders();
Trf797xRunDecoders();
}
