/**
* \brief Initializes the UartDma structure and the corresponding UART & DMA hardware.
* select value.
* The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.
* The DMA channels are freed automatically when no UART command processing.
*
* \param pUartd Pointer to a UartDma instance.
* \param pUartHw Associated UART peripheral.
* \param uartId UART peripheral identifier.
* \param uartMode UART peripheral identifier.*
* \param baud UART baud rate
* \param clk UART ref clock
* \param pXdmad Pointer to a Dmad instance.
*/
uint32_t UARTD_Configure( UartDma *pUartd ,
Uart *pUartHw ,
uint8_t uartId,
uint32_t uartMode,
uint32_t baud,
uint32_t clk,
sXdmad *pXdmad )
{
/* Initialize the UART structure */
pUartd->pUartHw = pUartHw;
pUartd->uartId = uartId;
pUartd->pXdmad = pXdmad;
/* Enable the UART Peripheral ,Execute a software reset of the UART, Configure UART in Master Mode*/
UART_Configure ( pUartHw, uartMode, baud, clk);
/* Enables the USART to transfer data. */
UART_SetTransmitterEnabled ( pUartHw , 1);
/* Enables the USART to receive data. */
UART_SetReceiverEnabled ( pUartHw , 1);
/* Driver initialize */
XDMAD_Initialize( pUartd->pXdmad, 0 );
/* Configure and enable interrupt on RC compare */
NVIC_ClearPendingIRQ(XDMAC_IRQn);
NVIC_SetPriority( XDMAC_IRQn ,1);
return 0;
}
uint32_t UARTD_DisableTxChannels( UartDma *pUartd, UartChannel *pTxCh)
{
assert(pTxCh);
/* Enables the USART to transfer data. */
UART_SetTransmitterEnabled ( pUartd->pUartHw , DISABLE);
XDMAD_StopTransfer(pUartd->pXdmad, pTxCh->ChNum);
XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, NULL, NULL);
/* Free allocated DMA channel for USART TX. */
if(XDMAD_FreeChannel( pUartd->pXdmad, pTxCh->ChNum) != XDMAD_OK) {
return USARTD_ERROR;
}
if (pTxCh->dmaProgrammingMode == XDMAD_LLI) {
free(pTxCh->pLLIview);
pTxCh->pLLIview = NULL;
}
pTxCh->sempaphore = 1;
memory_barrier();
return 0;
}
/**
* \brief UART transfer with interrupt in UART loop back mode
*/
static void UartTransfer(void)
{
uint8_t *pBuffer = &pTxBuffer[0];
PMC_EnablePeripheral(BASE_ID);
UART_Configure(BASE_UART, (UART_MR_PAR_NO | UART_MR_CHMODE_LOCAL_LOOPBACK),
115200, BOARD_MCK);
NVIC_ClearPendingIRQ(BASE_IRQ);
NVIC_SetPriority(BASE_IRQ ,1);
/* Enables the UART to transfer and receive data. */
UART_SetTransmitterEnabled (BASE_UART , 1);
UART_SetReceiverEnabled (BASE_UART , 1);
UART_EnableIt(BASE_UART, (UART_IER_RXRDY | UART_IER_OVRE | UART_IER_FRAME
| UART_IER_PARE));
/* Enable interrupt */
NVIC_EnableIRQ(BASE_IRQ);
while (*pBuffer != '\0') {
UART_PutChar(BASE_UART, *pBuffer);
pBuffer++;
}
UART_PutChar(BASE_UART, *pBuffer);
}
/**
* \brief This function initialize the appropriate DMA channel for Tx channel of
* UART
* \param pUartd Pointer to a UartDma instance.
* \param pTxCh Pointer to RxChannel configuration
* \returns 0 if the transfer has been started successfully;
* otherwise returns UARTD_ERROR_LOCK is the driver is in use, or UARTD_ERROR
* if the command is not valid.
*/
uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh)
{
Uart *pUartHw = pUartd->pUartHw;
uint32_t Channel;
/* Init USART Tx Channel. */
pUartd->pTxChannel = pTxCh;
/* Enables the USART to transfer data. */
UART_SetTransmitterEnabled ( pUartHw , ENABLE);
/* Allocate a DMA channel for UART TX. */
Channel = XDMAD_AllocateChannel( pUartd->pXdmad,
XDMAD_TRANSFER_MEMORY, pUartd->uartId);
if ( pTxCh->ChNum == XDMAD_ALLOC_FAILED ) {
return USARTD_ERROR;
}
pTxCh->ChNum = Channel ;
/* Setup callbacks for UART TX */
if(pUartd->pTxChannel->callback) {
XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum,
(XdmadTransferCallback)pTxCh->callback, pTxCh->pArgument);
} else {
XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)UARTD_Tx_Cb, pUartd);
}
if ( XDMAD_PrepareChannel( pUartd->pXdmad, pTxCh->ChNum ))
return USARTD_ERROR;
if (_configureUartTxDma(pUartd, pTxCh))
return USARTD_ERROR_LOCK;
/* Check if DMA IRQ is enable; if not Enable it */
if(!(NVIC_GetActive(XDMAC_IRQn))) {
/* Enable interrupt */
NVIC_EnableIRQ(XDMAC_IRQn);
}
return 0;
}
