void pic_irq_ack(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(UIC0SR, UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(UIC1SR, UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(UIC2SR, UIC_MASK(vec));
else if (vec >= 96)
mtdcr(UIC3SR, UIC_MASK(vec));
}
/*
* Install and free a interrupt handler.
*/
void pic_irq_enable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
else if (vec >= 96)
mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
debug("Install interrupt vector %d\n", vec);
}
/*
* Handle external interrupts
*/
void external_interrupt(struct pt_regs *regs)
{
u32 uic_msr;
/*
* Read masked interrupt status register to determine interrupt source
*/
uic_msr = mfdcr(UIC0MSR);
#if (UIC_MAX > 1)
if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
uic_interrupt(UIC1_DCR_BASE, 32);
#endif
#if (UIC_MAX > 2)
if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
uic_interrupt(UIC2_DCR_BASE, 64);
#endif
#if (UIC_MAX > 3)
if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
uic_interrupt(UIC3_DCR_BASE, 96);
#endif
mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
if (uic_msr & ~(UICB0_ALL))
uic_interrupt(UIC0_DCR_BASE, 0);
return;
}
void uic_irq_ack(unsigned int vec)
{
mtdcr(uic0sr, UIC_MASK(vec));
}
void rt_hw_interrupt_unmask(int vector)
{
mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
}
