/*set a random time for backing off of csma*/
static void csma_backoff_tick(uint32_t time_us)
{
if (csma_timer == NULL)
{
HAL_TIMER_SET_REL(US_TO_TICK(time_us - 80), csma_tick_cb, NULL, csma_timer);
DBG_ASSERT(csma_timer != NULL __DBG_LINE);
}
}
void initTimer1(uint32_t timeInUs, TIMER_PRESCALER prescaler, TimerIrqCallback callback)
{
timer1Counter = 0;
timer1IrqCallback = callback;
TCCR1A = 0;
// clear previous prescaler
CLRBITS(TCCR1B, 0x7);
// set prescaler
SETBIT(TCCR1B, prescaler);
// mode CTC
SETBIT(TCCR1B, 3);
// enable IRQ on match
SETBIT(TIMSK1, 1);
OCR1A = US_TO_TICK(timeInUs, getPrescalerDiv(prescaler));
}
static void tran_send(pbuf_t *pbuf)
{
DBG_ASSERT(pbuf != NULL __DBG_LINE);
#if M_SLOT_EN > 0
uint32_t send_need_time = LEN_TO_US(pbuf->data_len);
uint32_t slot_remain_time = TICK_TO_US(m_slot_get_remain_time());
#else
uint32_t send_need_time = 0;
uint32_t slot_remain_time = 0xFFFFFFFF;
#endif
if ((pbuf != NULL) && (slot_remain_time > send_need_time))
{
uint8_t stamp_size = 0;
#if M_SYNC_EN > 0
stamp_size = m_sync_txfilter(pbuf);
#endif
if (!phy_write_buf(pbuf, stamp_size))
{
#if M_TRAN_DGB_EN > 0
static uint32_t tx_write_fifo_fail_cnt = 0;
tx_write_fifo_fail_cnt++;
#endif
tran_send_failed();
return;
}
tran_state.tx_und_happend = FALSE;
if (!phy_send_data())
{
tran_send_failed();
return;
}
#if M_TRAN_DGB_EN > 0
m_tran_tracker.data_send_real++;
#endif
#if TXOK_INT_SIMU_EN > 0
HAL_TIMER_SET_REL(US_TO_TICK(LEN_TO_US(pbuf->data_len) + 10000),
tx_ok_error_timer,
NULL,
txok_timer);
DBG_ASSERT(txok_timer != NULL __DBG_LINE);
#endif
if (pbuf->attri.need_ack == TRUE)
{
tran_state.ack_needed = TRUE;
}
}
else
{
hal_int_state_t s;
HAL_ENTER_CRITICAL(s);
if (ack_timer != NULL)
{
hal_timer_cancel(&ack_timer);
}
tran_send_failed();
HAL_EXIT_CRITICAL(s);
}
}