int main(void)
{
uint8 i;
uint8 j;
uint8 OutputString[10];
pausems(5000);
UartSetBaudRate( B2400, PD1, PD0 );
EEAR = 0x01;
i = 'C';
EEDR = i;
/* Write the letter 'H' to address 0 of 511' */
asm volatile ("sbi %2, %0\n\t"
"sbi %2, %1\n\t"
:
:"I" (EEMWE), "I" (EEWE), "I" (0x1C)
);
// utoa(EEDR, OutputString, 10);
/* Wait until the EEPROM write has completed */
while( (EECR & (1 << EEWE) ) == 1)
{;
}
while(1)
{
EECR |= (1<<EERE);
pausems(10);
utoa(EEDR, OutputString, 10);
serout(OutputString);
}
}
uint8_t UartRx (void)
{
uint8_t i;
uint8_t Incoming;
uint8_t RxPin;
uint8_t *UartInfo;
uint8_t BaudRate;
UartInfo = UartSetBaudRate(0,0,0);
BaudRate = UartInfo[0];
RxPin = UartInfo[2];
/*make selected pin an input*/
DDRD &= ~(1<<RxPin);
/*Wait for a 'high' start bit*/
while((PIND & (1 << RxPin)) == 0)
{
PORTD &= ~(1<<RxPin);
}
/*Once received, wait 1.5 bit times*/
UartDelay(BaudRate+(BaudRate/2));
/*If it is high, write a 'low', if it is low, write a high*/
for(i = 0; i < BYTESIZE; i++)
{
Incoming >>= 1;
if((PIND && (1 << RxPin)) == 0)
{
Incoming += 0x80;
}
UartDelay(BaudRate);
}
return (Incoming);
}
bool BdPortInit(uint32 * BaseAddress, uint32 BaudRate)
{
#define PADCONF_CTS ((1 << 4) | (1 << 3) | (1 << 8))
#define PADCONF_RTS (0)
#define PADCONF_TX (0)
#define PADCONF_RX ((1 << 3) | (1 << 8))
uartBase = BaseAddress;
uint8 * HalpSCM = (uint8 *)OMAP_SCM_BASE;
uint8 * HalpCORE_CM = (uint8 *)OMAP_CORE_CM_BASE;
uint32 Value;
if (BaseAddress == (uint32 *)OMAP_UART1_BASE) {
// Power on the required function and interface units.
Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
Value |= CM_CORE_EN_UART1;
WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);
Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
Value |= CM_CORE_EN_UART1;
WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);
// Configure uart1 pads per documentation example
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_TX,
PADCONF_TX | (PADCONF_RTS << 16));
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_CTS,
PADCONF_CTS | (PADCONF_RX << 16));
}
else if (BaseAddress == (uint32 *)OMAP_UART2_BASE) {
// Power on the required function and interface units.
Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
Value |= CM_CORE_EN_UART2;
WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);
Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
Value |= CM_CORE_EN_UART2;
WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_CTS,
PADCONF_CTS | (PADCONF_RTS << 16));
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_TX,
PADCONF_TX | (PADCONF_RX << 16));
}
// Set the default baudrate.
UartSetBaudRate(BaseAddress, BaudRate);
// Set DLAB to zero. DLAB controls the meaning of the first two
// registers. When zero, the first register is used for all byte transfer
// and the second register controls device interrupts.
//
WriteReg8(BaseAddress + COM_LCR,
ReadReg8(BaseAddress + COM_LCR) & ~LCR_DLAB);
// Disable device interrupts. This implementation will handle state
// transitions by request only.
//
WriteReg8(BaseAddress + COM_IEN, 0);
// Reset and disable the FIFO queue.
// N.B. FIFO will be reenabled before returning from this routine.
//
WriteReg8(BaseAddress + COM_FCR, FCR_CLEAR_TRANSMIT | FCR_CLEAR_RECEIVE);
// Configure the Modem Control Register. Disabled device interrupts,
// turn off loopback.
//
WriteReg8(BaseAddress + COM_MCR,
ReadReg8(BaseAddress + COM_MCR) & MCR_INITIALIZE);
// Initialize the Modem Control Register. Indicate to the device that
// we are able to send and receive data.
//
WriteReg8(BaseAddress + COM_MCR, MCR_INITIALIZE);
// Enable the FIFO queues.
WriteReg8(BaseAddress + COM_FCR, FCR_ENABLE);
return true;
}
