DEFAULT_HANDLER(LPCOMP_IRQ);
DEFAULT_HANDLER(SWI0_IRQ);
DEFAULT_HANDLER(SWI1_IRQ);
DEFAULT_HANDLER(SWI2_IRQ);
DEFAULT_HANDLER(SWI3_IRQ);
DEFAULT_HANDLER(SWI4_IRQ);
DEFAULT_HANDLER(SWI5_IRQ);
#define VECTAB_ENTRY(x) [x##n] = nrf51_##x
/* appended to the end of the main vector table */
const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(POWER_CLOCK_IRQ),
VECTAB_ENTRY(RADIO_IRQ),
VECTAB_ENTRY(UART0_IRQ),
VECTAB_ENTRY(SPI0_TWI0_IRQ),
VECTAB_ENTRY(SPI1_TWI1_IRQ),
VECTAB_ENTRY(RESERVED_IRQ),
VECTAB_ENTRY(GPIOTE_IRQ),
VECTAB_ENTRY(ADC_IRQ),
VECTAB_ENTRY(TIMER0_IRQ),
VECTAB_ENTRY(TIMER1_IRQ),
VECTAB_ENTRY(TIMER2_IRQ),
VECTAB_ENTRY(RTC0_IRQ),
VECTAB_ENTRY(TEMP_IRQ),
VECTAB_ENTRY(RNG_IRQ),
VECTAB_ENTRY(ECB_IRQ),
DEFAULT_HANDLER(gpio_portq4);
DEFAULT_HANDLER(gpio_portq5);
DEFAULT_HANDLER(gpio_portq6);
DEFAULT_HANDLER(gpio_portq7);
DEFAULT_HANDLER(gpio_portr);
DEFAULT_HANDLER(gpio_ports);
DEFAULT_HANDLER(pwm1_gen0);
DEFAULT_HANDLER(pwm1_gen1);
DEFAULT_HANDLER(pwm1_gen2);
DEFAULT_HANDLER(pwm1_gen3);
DEFAULT_HANDLER(pwm1_fault);
#define VECTAB_ENTRY(x) stellaris_##x##_irq
const void * const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(gpio_porta), // GPIO Port A
VECTAB_ENTRY(gpio_portb), // GPIO Port B
VECTAB_ENTRY(gpio_portc), // GPIO Port C
VECTAB_ENTRY(gpio_portd), // GPIO Port D
VECTAB_ENTRY(gpio_porte), // GPIO Port E
VECTAB_ENTRY(uart0), // UART0 Rx and Tx
VECTAB_ENTRY(uart1), // UART1 Rx and Tx
VECTAB_ENTRY(ssi0), // SSI0 Rx and Tx
VECTAB_ENTRY(i2c0), // I2C0 Master and Slave
VECTAB_ENTRY(pwm_fault), // PWM Fault
VECTAB_ENTRY(pwm_gen0), // PWM Generator 0
VECTAB_ENTRY(pwm_gen1), // PWM Generator 1
VECTAB_ENTRY(pwm_gen2), // PWM Generator 2
VECTAB_ENTRY(quad_encoder0), // Quadrature Encoder 0
VECTAB_ENTRY(adc_seq0), // ADC Sequence 0
VECTAB_ENTRY(adc_seq1), // ADC Sequence 1
DEFAULT_HANDLER(TIM17_IRQ)
DEFAULT_HANDLER(I2C1_IRQ)
DEFAULT_HANDLER(I2C2_IRQ)
DEFAULT_HANDLER(SPI1_IRQ)
DEFAULT_HANDLER(SPI2_IRQ)
DEFAULT_HANDLER(USART1_IRQ)
DEFAULT_HANDLER(USART2_IRQ)
DEFAULT_HANDLER(USART3_4_IRQ)
DEFAULT_HANDLER(CEC_IRQ)
DEFAULT_HANDLER(USB_IRQ)
#define VECTAB_ENTRY(x) [x##n] = stm32_##x
/* appended to the end of the main vector table */
const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(WWDG_IRQ), // Window WatchDog Interrupt
VECTAB_ENTRY(PVD_IRQ), // PVD through EXTI Line detect Interrupt
VECTAB_ENTRY(RTC_IRQ), // RTC through EXTI Line Interrupt
VECTAB_ENTRY(FLASH_IRQ), // FLASH Interrupt
VECTAB_ENTRY(RCC_IRQ), // RCC Interrupt
VECTAB_ENTRY(EXTI0_1_IRQ), // EXTI Line 0 and 1 Interrupts
VECTAB_ENTRY(EXTI2_3_IRQ), // EXTI Line 2 and 3 Interrupts
VECTAB_ENTRY(EXTI4_15_IRQ), // EXTI Line 4 to 15 Interrupts
VECTAB_ENTRY(TS_IRQ), // Touch sense controller Interrupt
VECTAB_ENTRY(DMA1_Channel1_IRQ), // DMA1 Channel 1 Interrupt
VECTAB_ENTRY(DMA1_Channel2_3_IRQ), // DMA1 Channel 2 and Channel 3 Interrupts
VECTAB_ENTRY(DMA1_Channel4_5_6_7_IRQ), // DMA1 Channels 4-7 Interrupts
VECTAB_ENTRY(ADC1_COMP_IRQ), // ADC1, COMP1 and COMP2 Interrupts
VECTAB_ENTRY(TIM1_BRK_UP_TRG_COM_IRQ), // TIM1 Break, Update, Trigger and Commutation Interrupts
VECTAB_ENTRY(TIM1_CC_IRQ), // TIM1 Capture Compare Interrupt
VECTAB_ENTRY(TIM2_IRQ), // TIM2 Interrupt
DEFAULT_HANDLER(PDM_IRQ);
DEFAULT_HANDLER(MWU_IRQ);
DEFAULT_HANDLER(PWM1_IRQ);
DEFAULT_HANDLER(PWM2_IRQ);
DEFAULT_HANDLER(SPIM2_SPIS2_SPI2_IRQ);
DEFAULT_HANDLER(RTC2_IRQ);
DEFAULT_HANDLER(I2S_IRQ);
DEFAULT_HANDLER(FPU_IRQ);
#define VECTAB_ENTRY(x) [x##n] = nrf52_##x
/* appended to the end of the main vector table */
const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(POWER_CLOCK_IRQ),
VECTAB_ENTRY(RADIO_IRQ),
VECTAB_ENTRY(UARTE0_UART0_IRQ),
VECTAB_ENTRY(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQ),
VECTAB_ENTRY(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQ),
VECTAB_ENTRY(NFCT_IRQ),
VECTAB_ENTRY(GPIOTE_IRQ),
VECTAB_ENTRY(SAADC_IRQ),
VECTAB_ENTRY(TIMER0_IRQ),
VECTAB_ENTRY(TIMER1_IRQ),
VECTAB_ENTRY(TIMER2_IRQ),
VECTAB_ENTRY(RTC0_IRQ),
VECTAB_ENTRY(TEMP_IRQ),
VECTAB_ENTRY(RNG_IRQ),
VECTAB_ENTRY(ECB_IRQ),
VECTAB_ENTRY(CCM_AAR_IRQ),
DEFAULT_HANDLER(I2C3_EV_IRQ);
DEFAULT_HANDLER(I2C3_ER_IRQ);
DEFAULT_HANDLER(OTG_HS_EP1_OUT_IRQ);
DEFAULT_HANDLER(OTG_HS_EP1_IN_IRQ);
DEFAULT_HANDLER(OTG_HS_WKUP_IRQ);
DEFAULT_HANDLER(OTG_HS_IRQ);
DEFAULT_HANDLER(DCMI_IRQ);
DEFAULT_HANDLER(CRYP_IRQ);
DEFAULT_HANDLER(HASH_RNG_IRQ);
#define VECTAB_ENTRY(x) [x##n] = stm32_##x
/* appended to the end of the main vector table */
const void * const __SECTION(".text.boot.vectab2") vectab2[] =
{
VECTAB_ENTRY(WWDG_IRQ), /* Window WatchDog Interrupt */
VECTAB_ENTRY(PVD_IRQ), /* PVD through EXTI Line detection Interrupt */
VECTAB_ENTRY(TAMP_STAMP_IRQ), /* Tamper and TimeStamp interrupts through the EXTI line */
VECTAB_ENTRY(RTC_WKUP_IRQ), /* RTC Wakeup interrupt through the EXTI line */
VECTAB_ENTRY(FLASH_IRQ), /* FLASH global Interrupt */
VECTAB_ENTRY(RCC_IRQ), /* RCC global Interrupt */
VECTAB_ENTRY(EXTI0_IRQ), /* EXTI Line0 Interrupt */
VECTAB_ENTRY(EXTI1_IRQ), /* EXTI Line1 Interrupt */
VECTAB_ENTRY(EXTI2_IRQ), /* EXTI Line2 Interrupt */
VECTAB_ENTRY(EXTI3_IRQ), /* EXTI Line3 Interrupt */
VECTAB_ENTRY(EXTI4_IRQ), /* EXTI Line4 Interrupt */
VECTAB_ENTRY(DMA1_Stream0_IRQ), /* DMA1 Stream 0 global Interrupt */
VECTAB_ENTRY(DMA1_Stream1_IRQ), /* DMA1 Stream 1 global Interrupt */
VECTAB_ENTRY(DMA1_Stream2_IRQ), /* DMA1 Stream 2 global Interrupt */
VECTAB_ENTRY(DMA1_Stream3_IRQ), /* DMA1 Stream 3 global Interrupt */
VECTAB_ENTRY(DMA1_Stream4_IRQ), /* DMA1 Stream 4 global Interrupt */
DEFAULT_HANDLER(LTDC_IRQ);
DEFAULT_HANDLER(LTDC_ER_IRQ);
DEFAULT_HANDLER(DMA2D_IRQ);
DEFAULT_HANDLER(SAI2_IRQ);
DEFAULT_HANDLER(QUADSPI_IRQ);
DEFAULT_HANDLER(LPTIM1_IRQ);
DEFAULT_HANDLER(CEC_IRQ);
DEFAULT_HANDLER(I2C4_EV_IRQ);
DEFAULT_HANDLER(I2C4_ER_IRQ);
DEFAULT_HANDLER(SPDIF_RX_IRQ);
#define VECTAB_ENTRY(x) [x##n] = stm32_##x
/* appended to the end of the main vector table */
const void * const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(WWDG_IRQ), /*!< Window WatchDog Interrupt */
VECTAB_ENTRY(PVD_IRQ), /*!< PVD through EXTI Line detection Interrupt */
VECTAB_ENTRY(TAMP_STAMP_IRQ), /*!< Tamper and TimeStamp interrupts through the EXTI line */
VECTAB_ENTRY(RTC_WKUP_IRQ), /*!< RTC Wakeup interrupt through the EXTI line */
VECTAB_ENTRY(FLASH_IRQ), /*!< FLASH global Interrupt */
VECTAB_ENTRY(RCC_IRQ), /*!< RCC global Interrupt */
VECTAB_ENTRY(EXTI0_IRQ), /*!< EXTI Line0 Interrupt */
VECTAB_ENTRY(EXTI1_IRQ), /*!< EXTI Line1 Interrupt */
VECTAB_ENTRY(EXTI2_IRQ), /*!< EXTI Line2 Interrupt */
VECTAB_ENTRY(EXTI3_IRQ), /*!< EXTI Line3 Interrupt */
VECTAB_ENTRY(EXTI4_IRQ), /*!< EXTI Line4 Interrupt */
VECTAB_ENTRY(DMA1_Stream0_IRQ), /*!< DMA1 Stream 0 global Interrupt */
VECTAB_ENTRY(DMA1_Stream1_IRQ), /*!< DMA1 Stream 1 global Interrupt */
VECTAB_ENTRY(DMA1_Stream2_IRQ), /*!< DMA1 Stream 2 global Interrupt */
VECTAB_ENTRY(DMA1_Stream3_IRQ), /*!< DMA1 Stream 3 global Interrupt */
VECTAB_ENTRY(DMA1_Stream4_IRQ), /*!< DMA1 Stream 4 global Interrupt */
