u32 vidc_720p_engine_reset(u32 ch_id,
enum vidc_720p_endian dma_endian,
enum vidc_720p_interrupt_level_selection interrupt_sel,
u32 interrupt_mask
)
{
u32 op_done = 0;
u32 counter = 0;
VIDC_LOGERR_STRING("ENG-RESET!!");
/* issue the engine reset command */
vidc_720p_submit_command(ch_id, VIDC_720P_CMD_MFC_ENGINE_RESET);
do {
VIDC_BUSY_WAIT(20);
VIDC_IO_IN(REG_982553, &op_done);
counter++;
} while (!op_done && counter < 10);
if (!op_done) {
/* Reset fails */
return false ;
}
/* write invalid channel id */
VIDC_IO_OUT(REG_97293, 4);
/* Set INT_PULSE_SEL */
if (interrupt_sel == VIDC_720P_INTERRUPT_LEVEL_SEL)
VIDC_IO_OUT(REG_491082, 0);
else
VIDC_IO_OUT(REG_491082, 1);
if (!interrupt_mask) {
/* Disable interrupt */
VIDC_IO_OUT(REG_609676, 1);
} else {
/* Enable interrupt */
VIDC_IO_OUT(REG_609676, 0);
}
/* Clear any pending interrupt */
VIDC_IO_OUT(REG_614776, 1);
/* Set INT_ENABLE_REG */
VIDC_IO_OUT(REG_418173, interrupt_mask);
/*Sets the DMA endianness */
VIDC_IO_OUT(REG_736316, dma_endian);
/*Restore ARM endianness */
VIDC_IO_OUT(REG_215724, 0);
/* retun engine reset success */
return true ;
}
u32 vidc_720p_do_sw_reset(void)
{
u32 fw_start = 0;
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_224135, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_193553, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_141269, 1);
VIDC_BUSY_WAIT(15);
VIDC_IO_OUT(REG_141269, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_IN(REG_193553, &fw_start);
if (!fw_start) {
DBG("\n VIDC-SW-RESET-FAILS!");
return false;
}
return true;
}
u32 vidc_720p_do_sw_reset(void)
{
u32 n_fw_start = 0;
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_224135, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_193553, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_OUT(REG_141269, 1);
VIDC_BUSY_WAIT(15);
VIDC_IO_OUT(REG_141269, 0);
VIDC_BUSY_WAIT(5);
VIDC_IO_IN(REG_193553, &n_fw_start);
if (!n_fw_start) {
DBG("\n VIDC-SW-RESET-FAILS!");
return FALSE;
}
return TRUE;
}
