{ PCIXenPlatformState *s = opaque; platform_fixed_ioport_writeb(s, 0, s->flags); return 0; } static const VMStateDescription vmstate_xen_platform = { .name = "platform", .version_id = 4, .minimum_version_id = 4, .minimum_version_id_old = 4, .post_load = xen_platform_post_load, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState), VMSTATE_UINT8(flags, PCIXenPlatformState), VMSTATE_END_OF_LIST() } }; static int xen_platform_initfn(PCIDevice *dev) { PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev); uint8_t *pci_conf; pci_conf = d->pci_dev.config; pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); pci_config_set_prog_interface(pci_conf, 0);
pci_conf[0xa6] = 0x00; pci_conf[0xa7] = 0x00; pci_conf[0xa8] = 0x0f; pci_conf[0xaa] = 0x00; pci_conf[0xab] = 0x00; pci_conf[0xac] = 0x00; pci_conf[0xae] = 0x00; } static const VMStateDescription vmstate_piix4 = { .name = "PIIX4", .version_id = 2, .minimum_version_id = 2, .minimum_version_id_old = 2, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PIIX4State), VMSTATE_END_OF_LIST() } }; static int piix4_initfn(PCIDevice *dev) { PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev); isa_bus_new(&d->dev.qdev, pci_address_space_io(dev)); piix4_dev = &d->dev; qemu_register_reset(piix4_reset, d); return 0; } int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
} busmaster = pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_MASTER; i->ehci.dma = busmaster ? pci_dma_context(dev) : NULL; } static Property ehci_pci_properties[] = { DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128), DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_ehci_pci = { .name = "ehci", .version_id = 2, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState), VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState), VMSTATE_END_OF_LIST() } }; static void ehci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); EHCIPCIInfo *i = data; k->init = usb_ehci_pci_initfn; k->vendor_id = i->vendor_id; k->device_id = i->device_id; k->revision = i->revision;
memory_region_init(&s->bar, NULL, "macio", 0x80000); object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA); qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default()); object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL); s->dbdma = DBDMA_init(&dbdma_mem); memory_region_add_subregion(&s->bar, 0x08000, dbdma_mem); } static const VMStateDescription vmstate_macio_oldworld = { .name = "macio-oldworld", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState), VMSTATE_END_OF_LIST() } }; static void macio_oldworld_class_init(ObjectClass *oc, void *data) { PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); pdc->init = macio_oldworld_initfn; pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201; dc->vmsd = &vmstate_macio_oldworld; } static const VMStateDescription vmstate_macio_newworld = {
if (!grp->res_reserve.io) { pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND, PCI_COMMAND_IO); d->wmask[PCI_IO_BASE] = 0; d->wmask[PCI_IO_LIMIT] = 0; } } static const VMStateDescription vmstate_rp_dev = { .name = "pcie-root-port", .priority = MIG_PRI_PCI_BUS, .version_id = 1, .minimum_version_id = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj, GenPCIERootPort, gen_rp_test_migrate_msix), VMSTATE_END_OF_LIST() } }; static Property gen_rp_props[] = { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true), DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, res_reserve.bus, -1), DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
ohci_hard_reset(s); } static Property ohci_pci_properties[] = { DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus), DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_ohci = { .name = "ohci", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState), VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState), VMSTATE_END_OF_LIST() } }; static void ohci_pci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->realize = usb_ohci_realize_pci; k->exit = usb_ohci_exit; k->vendor_id = PCI_VENDOR_ID_APPLE; k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; k->class_id = PCI_CLASS_SERIAL_USB;
static int mch_post_load(void *opaque, int version_id) { MCHPCIState *mch = opaque; mch_update(mch); return 0; } static const VMStateDescription vmstate_mch = { .name = "mch", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .post_load = mch_post_load, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(d, MCHPCIState), VMSTATE_UINT8(smm_enabled, MCHPCIState), VMSTATE_END_OF_LIST() } }; static void mch_reset(DeviceState *qdev) { PCIDevice *d = PCI_DEVICE(qdev); MCHPCIState *mch = MCH_PCI_DEVICE(d); pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
for (i = 0; i < pci->ports; i++) { s = pci->state + i; serial_exit_core(s); memory_region_del_subregion(&pci->iobar, &s->io); g_free(pci->name[i]); } qemu_free_irqs(pci->irqs, pci->ports); } static const VMStateDescription vmstate_pci_serial = { .name = "pci-serial", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PCISerialState), VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_pci_multi_serial = { .name = "pci-serial-multi", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState), VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS, 0, vmstate_serial, SerialState), VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS), VMSTATE_END_OF_LIST()
br = PCI_BRIDGE(d); qdev = DEVICE(d); pci_bridge_map_irq(br, bus_name, map_irq); qdev_prop_set_uint8(qdev, "port", port); qdev_init_nofail(qdev); return PCIE_PORT(d); } static const VMStateDescription vmstate_xio3130_upstream = { .name = "xio3130-express-upstream-port", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort), VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } }; static void xio3130_upstream_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->is_express = 1; k->is_bridge = 1; k->config_write = xio3130_upstream_write_config; k->realize = xio3130_upstream_realize;
d->timer1_preload = val & 0xfffff; else if (addr == 4) d->timer2_preload = val & 0xfffff; d->unlock_state = 0; } } } static const VMStateDescription vmstate_i6300esb = { .name = "i6300esb_wdt", .version_id = sizeof(I6300State), .minimum_version_id = sizeof(I6300State), .minimum_version_id_old = sizeof(I6300State), .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(dev, I6300State), VMSTATE_INT32(reboot_enabled, I6300State), VMSTATE_INT32(clock_scale, I6300State), VMSTATE_INT32(int_type, I6300State), VMSTATE_INT32(free_run, I6300State), VMSTATE_INT32(locked, I6300State), VMSTATE_INT32(enabled, I6300State), VMSTATE_TIMER(timer, I6300State), VMSTATE_UINT32(timer1_preload, I6300State), VMSTATE_UINT32(timer2_preload, I6300State), VMSTATE_INT32(stage, I6300State), VMSTATE_INT32(unlock_state, I6300State), VMSTATE_INT32(previous_reboot_flag, I6300State), VMSTATE_END_OF_LIST() } };
static int raven_init(PCIDevice *d) { d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer d->config[0x34] = 0x00; // capabilities_pointer return 0; } static const VMStateDescription vmstate_raven = { .name = "raven", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, RavenPCIState), VMSTATE_END_OF_LIST() }, }; static void raven_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); k->init = raven_init; k->vendor_id = PCI_VENDOR_ID_MOTOROLA; k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; k->revision = 0x00; k->class_id = PCI_CLASS_BRIDGE_HOST; dc->desc = "PReP Host Bridge - Motorola Raven";
static int xen_platform_post_load(void *opaque, int version_id) { PCIXenPlatformState *s = opaque; platform_fixed_ioport_writeb(s, 0, s->flags); return 0; } static const VMStateDescription vmstate_xen_platform = { .name = "platform", .version_id = 4, .minimum_version_id = 4, .post_load = xen_platform_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCIXenPlatformState), VMSTATE_UINT8(flags, PCIXenPlatformState), VMSTATE_END_OF_LIST() } }; static int xen_platform_initfn(PCIDevice *dev) { PCIXenPlatformState *d = XEN_PLATFORM(dev); uint8_t *pci_conf; pci_conf = dev->config; pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); pci_config_set_prog_interface(pci_conf, 0);
static void pci_tnetw1130_uninit(PCIDevice *pci_dev) { TNETW1130State *s = DO_UPCAST(TNETW1130State, dev, pci_dev); memory_region_destroy(&s->mmio_bar0); memory_region_destroy(&s->mmio_bar1); qemu_del_nic(s->tnetw1130.nic); } static const VMStateDescription vmstate_pci_tnetw1130 = { .name = "tnetw1130", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(dev, TNETW1130State), // TODO: entries for tnetw1130 are missing here. //~ VMSTATE_UINT32(rxbuf_size, E1000State), //~ VMSTATE_UINT32(rxbuf_min_shift, E1000State), //~ VMSTATE_UINT32(eecd_state.val_in, E1000State), //~ VMSTATE_UINT16(eecd_state.bitnum_in, E1000State), //~ VMSTATE_UINT16(eecd_state.bitnum_out, E1000State), //~ VMSTATE_UINT16(eecd_state.reading, E1000State), //~ VMSTATE_UINT32(eecd_state.old_eecd, E1000State), //~ VMSTATE_UINT8(tx.ipcss, E1000State), //~ VMSTATE_UINT8(tx.ipcso, E1000State), //~ VMSTATE_UINT16(tx.ipcse, E1000State), //~ VMSTATE_UINT8(tx.tucss, E1000State), //~ VMSTATE_UINT8(tx.tucso, E1000State), //~ VMSTATE_UINT16(tx.tucse, E1000State), //~ VMSTATE_UINT32(tx.paylen, E1000State),
pci_bridge_reset(qdev); shpc_reset(dev); } static Property pci_bridge_dev_properties[] = { /* Note: 0 is not a legal chassis number. */ DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0), DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true), DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription pci_bridge_dev_vmstate = { .name = "pci_bridge", .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev), SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev), VMSTATE_END_OF_LIST() } }; static void pci_bridge_dev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = pci_bridge_dev_initfn; k->exit = pci_bridge_dev_exitfn; k->config_write = pci_bridge_dev_write_config; k->vendor_id = PCI_BRIDGE_DEV_VENDOR_ID; k->device_id = PCI_BRIDGE_DEV_DEVICE_ID; k->class_id = PCI_CLASS_BRIDGE_PCI;
val |= pcnet_aprom_readb(d, addr); } #ifdef PCNET_DEBUG_IO printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, val); #endif return val; } static const VMStateDescription vmstate_pci_pcnet = { .name = "pcnet", .version_id = 3, .minimum_version_id = 2, .minimum_version_id_old = 2, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState), VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), VMSTATE_END_OF_LIST() } }; /* PCI interface */ static CPUWriteMemoryFunc * const pcnet_mmio_write[] = { &pcnet_mmio_writeb, &pcnet_mmio_writew, &pcnet_mmio_writel }; static CPUReadMemoryFunc * const pcnet_mmio_read[] = { &pcnet_mmio_readb,
static int mch_post_load(void *opaque, int version_id) { MCHPCIState *mch = opaque; mch_update(mch); return 0; } static const VMStateDescription vmstate_mch = { .name = "mch", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .post_load = mch_post_load, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), VMSTATE_UINT8(smm_enabled, MCHPCIState), VMSTATE_END_OF_LIST() } }; static void mch_reset(DeviceState *qdev) { PCIDevice *d = PCI_DEVICE(qdev); MCHPCIState *mch = MCH_PCI_DEVICE(d); pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
char *path = object_get_canonical_path_component(val); error_setg(errp, "can't use already busy memdev: %s", path); g_free(path); } else { qdev_prop_allow_set_link_before_realize(obj, name, val, errp); } } static const VMStateDescription ivshmem_plain_vmsd = { .name = TYPE_IVSHMEM_PLAIN, .version_id = 0, .minimum_version_id = 0, .pre_load = ivshmem_pre_load, .post_load = ivshmem_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), VMSTATE_UINT32(intrstatus, IVShmemState), VMSTATE_UINT32(intrmask, IVShmemState), VMSTATE_END_OF_LIST() }, }; static Property ivshmem_plain_properties[] = { DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), DEFINE_PROP_END_OF_LIST(), }; static void ivshmem_plain_init(Object *obj) { IVShmemState *s = IVSHMEM_PLAIN(obj);
pci_bridge_reset(qdev); shpc_reset(dev); } static Property pci_bridge_dev_properties[] = { /* Note: 0 is not a legal chassis number. */ DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0), DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true), DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription pci_bridge_dev_vmstate = { .name = "pci_bridge", .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), SHPC_VMSTATE(shpc, PCIDevice), VMSTATE_END_OF_LIST() } }; static void pci_bridge_dev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); k->init = pci_bridge_dev_initfn; k->exit = pci_bridge_dev_exitfn; k->config_write = pci_bridge_dev_write_config; k->vendor_id = PCI_VENDOR_ID_REDHAT;
for (int i=0; i<d->fake_pci.num_resources; ++i) { memory_region_destroy(&d->io[i]); } return 0; } static VMStateDescription vmstate_pci_fake = { .name = "fakepci", .version_id = 3, .minimum_version_id = 3, .minimum_version_id_old = 3, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(dev, PCIFakeState), VMSTATE_END_OF_LIST() } }; static Property fakepci_properties[] = { DEFINE_PROP_END_OF_LIST(), }; static void fakepci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = pci_fake_init;