Пример #1
0
    uint32_t write_word_n;
    uint16_t write_word_l;
    uint16_t write_word_h;
    uint32_t read_word_prev_offset;
    uint32_t read_word_n;
    uint32_t read_long;

    uint32_t mode_16bit;
} lan9118_state;

static const VMStateDescription vmstate_lan9118 = {
    .name = "lan9118",
    .version_id = 2,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PTIMER(timer, lan9118_state),
        VMSTATE_UINT32(irq_cfg, lan9118_state),
        VMSTATE_UINT32(int_sts, lan9118_state),
        VMSTATE_UINT32(int_en, lan9118_state),
        VMSTATE_UINT32(fifo_int, lan9118_state),
        VMSTATE_UINT32(rx_cfg, lan9118_state),
        VMSTATE_UINT32(tx_cfg, lan9118_state),
        VMSTATE_UINT32(hw_cfg, lan9118_state),
        VMSTATE_UINT32(pmt_ctrl, lan9118_state),
        VMSTATE_UINT32(gpio_cfg, lan9118_state),
        VMSTATE_UINT32(gpt_cfg, lan9118_state),
        VMSTATE_UINT32(word_swap, lan9118_state),
        VMSTATE_UINT32(free_timer_start, lan9118_state),
        VMSTATE_UINT32(mac_cmd, lan9118_state),
        VMSTATE_UINT32(mac_data, lan9118_state),
        VMSTATE_UINT32(afc_cfg, lan9118_state),
Пример #2
0
    ptimer_set_freq(s->ptimer, s->freq_hz);

    timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s,
                                        DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4, timer_regs);

    return 0;
}

static const VMStateDescription vmstate_lm32_timer = {
    .name = "lm32-timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_PTIMER(ptimer, LM32TimerState),
        VMSTATE_UINT32(freq_hz, LM32TimerState),
        VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static SysBusDeviceInfo lm32_timer_info = {
    .init = lm32_timer_init,
    .qdev.name  = "lm32-timer",
    .qdev.size  = sizeof(LM32TimerState),
    .qdev.vmsd  = &vmstate_lm32_timer,
    .qdev.reset = timer_reset,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32(
            "frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY
Пример #3
0
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    s->int_level = 1;
    arm_timer_update(s);
}

static const VMStateDescription vmstate_arm_timer = {
    .name = "arm_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(control, arm_timer_state),
        VMSTATE_UINT32(limit, arm_timer_state),
        VMSTATE_INT32(int_level, arm_timer_state),
        VMSTATE_PTIMER(timer, arm_timer_state),
        VMSTATE_END_OF_LIST()
    }
};

static arm_timer_state *arm_timer_init(uint32_t freq)
{
    arm_timer_state *s;
    QEMUBH *bh;

    s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
    s->freq = freq;
    s->control = TIMER_CTRL_IE;

    bh = qemu_bh_new(arm_timer_tick, s);
    s->timer = ptimer_init(bh);
Пример #4
0
    memory_region_init_io(&s->regs_region, &sysctl_mmio_ops, s,
                          "milkymist-sysctl", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);

    return 0;
}

static const VMStateDescription vmstate_milkymist_sysctl = {
    .name = "milkymist-sysctl",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
        VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
        VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
        VMSTATE_END_OF_LIST()
    }
};

static SysBusDeviceInfo milkymist_sysctl_info = {
    .init = milkymist_sysctl_init,
    .qdev.name  = "milkymist-sysctl",
    .qdev.size  = sizeof(MilkymistSysctlState),
    .qdev.vmsd  = &vmstate_milkymist_sysctl,
    .qdev.reset = milkymist_sysctl_reset,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
        freq_hz, 80000000),
        DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
Пример #5
0
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/ptimer.h"
#include "qemu/main-loop.h"
#include "qemu/log.h"

#include "hw/timer/digic-timer.h"

static const VMStateDescription vmstate_digic_timer = {
    .name = "digic.timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PTIMER(ptimer, DigicTimerState),
        VMSTATE_UINT32(control, DigicTimerState),
        VMSTATE_UINT32(relvalue, DigicTimerState),
        VMSTATE_END_OF_LIST()
    }
};

static void digic_timer_reset(DeviceState *dev)
{
    DigicTimerState *s = DIGIC_TIMER(dev);

    ptimer_stop(s->ptimer);
    s->control = 0;
    s->relvalue = 0;
}
Пример #6
0
    .write = imx_epit_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_imx_timer_epit = {
    .name = TYPE_IMX_EPIT,
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cr, IMXEPITState),
        VMSTATE_UINT32(sr, IMXEPITState),
        VMSTATE_UINT32(lr, IMXEPITState),
        VMSTATE_UINT32(cmp, IMXEPITState),
        VMSTATE_UINT32(cnt, IMXEPITState),
        VMSTATE_UINT32(freq, IMXEPITState),
        VMSTATE_PTIMER(timer_reload, IMXEPITState),
        VMSTATE_PTIMER(timer_cmp, IMXEPITState),
        VMSTATE_END_OF_LIST()
    }
};

static void imx_epit_realize(DeviceState *dev, Error **errp)
{
    IMXEPITState *s = IMX_EPIT(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    QEMUBH *bh;

    DPRINTF("\n");

    sysbus_init_irq(sbd, &s->irq);
    memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT,
Пример #7
0
    .minimum_version_id = 3,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cr, IMXGPTState),
        VMSTATE_UINT32(pr, IMXGPTState),
        VMSTATE_UINT32(sr, IMXGPTState),
        VMSTATE_UINT32(ir, IMXGPTState),
        VMSTATE_UINT32(ocr1, IMXGPTState),
        VMSTATE_UINT32(ocr2, IMXGPTState),
        VMSTATE_UINT32(ocr3, IMXGPTState),
        VMSTATE_UINT32(icr1, IMXGPTState),
        VMSTATE_UINT32(icr2, IMXGPTState),
        VMSTATE_UINT32(cnt, IMXGPTState),
        VMSTATE_UINT32(next_timeout, IMXGPTState),
        VMSTATE_UINT32(next_int, IMXGPTState),
        VMSTATE_UINT32(freq, IMXGPTState),
        VMSTATE_PTIMER(timer, IMXGPTState),
        VMSTATE_END_OF_LIST()
    }
};

static const IMXClk imx_gpt_clocks[] = {
    NOCLK,    /* 000 No clock source */
    IPG,      /* 001 ipg_clk, 532MHz*/
    IPG,      /* 010 ipg_clk_highfreq */
    NOCLK,    /* 011 not defined */
    CLK_32k,  /* 100 ipg_clk_32k */
    NOCLK,    /* 101 not defined */
    NOCLK,    /* 110 not defined */
    NOCLK,    /* 111 not defined */
};
Пример #8
0
    .read = rtt_read,
    .write = rtt_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_rtt = {
    .name = "rtt_ssp",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(mr, rtt_state),
        VMSTATE_UINT32(ar, rtt_state),
        VMSTATE_UINT32(vr, rtt_state),
        VMSTATE_UINT32(sr, rtt_state),
        VMSTATE_PTIMER(timer,rtt_state),
        VMSTATE_END_OF_LIST()
    }
};

static int rtt_init(SysBusDevice *dev)
{
    rtt_state *s = FROM_SYSBUS(rtt_state, dev);
    QEMUBH *bh;

    memory_region_init_io(&s->iomem, OBJECT(s), &rtt_ops, s, "rtt", 0x20);
    sysbus_init_mmio(dev, &s->iomem);
    sysbus_init_irq(dev, &s->irq);
    //s->ssi = ssi_create_bus(&dev->qdev, "ssi");
    //rtt_reset(s);
    //vmstate_register(&dev->qdev, -1, &vmstate_rtt, s);