}
bool smbus_vmstate_needed(SMBusDevice *dev)
{
return dev->mode != SMBUS_IDLE;
}
const VMStateDescription vmstate_smbus_device = {
.name = TYPE_SMBUS_DEVICE,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_I2C_SLAVE(i2c, SMBusDevice),
VMSTATE_INT32(mode, SMBusDevice),
VMSTATE_INT32(data_len, SMBusDevice),
VMSTATE_UINT8_ARRAY(data_buf, SMBusDevice, SMBUS_DATA_MAX_LEN),
VMSTATE_END_OF_LIST()
}
};
static const TypeInfo smbus_device_type_info = {
.name = TYPE_SMBUS_DEVICE,
.parent = TYPE_I2C_SLAVE,
.instance_size = sizeof(SMBusDevice),
.abstract = true,
.class_size = sizeof(SMBusDeviceClass),
.class_init = smbus_device_class_init,
};
static void smbus_device_register_types(void)
{
{
UartState *s = opaque;
uart_parameters_setup(s);
uart_update_status(s);
return 0;
}
static const VMStateDescription vmstate_cadence_uart = {
.name = "cadence_uart",
.version_id = 2,
.minimum_version_id = 2,
.post_load = cadence_uart_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE),
VMSTATE_UINT32(rx_count, UartState),
VMSTATE_UINT32(tx_count, UartState),
VMSTATE_UINT32(rx_wpos, UartState),
VMSTATE_TIMER(fifo_trigger_handle, UartState),
VMSTATE_END_OF_LIST()
}
};
static void cadence_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = cadence_uart_init;
} LAN9118Packet;
static const VMStateDescription vmstate_lan9118_packet = {
.name = "lan9118_packet",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(state, LAN9118Packet),
VMSTATE_UINT32(cmd_a, LAN9118Packet),
VMSTATE_UINT32(cmd_b, LAN9118Packet),
VMSTATE_INT32(buffer_size, LAN9118Packet),
VMSTATE_INT32(offset, LAN9118Packet),
VMSTATE_INT32(pad, LAN9118Packet),
VMSTATE_INT32(fifo_used, LAN9118Packet),
VMSTATE_INT32(len, LAN9118Packet),
VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
VMSTATE_END_OF_LIST()
}
};
typedef struct {
SysBusDevice busdev;
NICState *nic;
NICConf conf;
qemu_irq irq;
MemoryRegion mmio;
ptimer_state *timer;
uint32_t irq_cfg;
uint32_t int_sts;
uint32_t int_en;
{
CadenceUARTState *s = opaque;
uart_parameters_setup(s);
uart_update_status(s);
return 0;
}
static const VMStateDescription vmstate_cadence_uart = {
.name = "cadence_uart",
.version_id = 2,
.minimum_version_id = 2,
.post_load = cadence_uart_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
CADENCE_UART_RX_FIFO_SIZE),
VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
CADENCE_UART_TX_FIFO_SIZE),
VMSTATE_UINT32(rx_count, CadenceUARTState),
VMSTATE_UINT32(tx_count, CadenceUARTState),
VMSTATE_UINT32(rx_wpos, CadenceUARTState),
VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
VMSTATE_END_OF_LIST()
}
};
static void cadence_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = cadence_uart_realize;
return 0;
}
static const VMStateDescription vmstate_milkymist_memcard = {
.name = "milkymist-memcard",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
VMSTATE_INT32(response_len, MilkymistMemcardState),
VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
VMSTATE_INT32(enabled, MilkymistMemcardState),
VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
VMSTATE_END_OF_LIST()
}
};
static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = milkymist_memcard_init;
dc->reset = milkymist_memcard_reset;
dc->vmsd = &vmstate_milkymist_memcard;
}
};
static CPUWriteMemoryFunc * const cs_mem_write[3] = {
cs_mem_writel,
cs_mem_writel,
cs_mem_writel,
};
static const VMStateDescription vmstate_cs4231 = {
.name ="cs4231",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS),
VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS),
VMSTATE_END_OF_LIST()
}
};
static int cs4231_init1(SysBusDevice *dev)
{
int io;
CSState *s = FROM_SYSBUS(CSState, dev);
io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, CS_SIZE, io);
sysbus_init_irq(dev, &s->irq);
return 0;
#define IPL_PSW_MASK (PSW_MASK_32 | PSW_MASK_64)
static bool iplb_extended_needed(void *opaque)
{
S390IPLState *ipl = S390_IPL(object_resolve_path(TYPE_S390_IPL, NULL));
return ipl->iplbext_migration;
}
static const VMStateDescription vmstate_iplb_extended = {
.name = "ipl/iplb_extended",
.version_id = 0,
.minimum_version_id = 0,
.needed = iplb_extended_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(reserved_ext, IplParameterBlock, 4096 - 200),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_iplb = {
.name = "ipl/iplb",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(reserved1, IplParameterBlock, 110),
VMSTATE_UINT16(devno, IplParameterBlock),
VMSTATE_UINT8_ARRAY(reserved2, IplParameterBlock, 88),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
DEFINE_PROP_DRIVE("drive", Flash, blk),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_m25p80 = {
.name = "m25p80",
.version_id = 0,
.minimum_version_id = 0,
.pre_save = m25p80_pre_save,
.fields = (VMStateField[]) {
VMSTATE_UINT8(state, Flash),
VMSTATE_UINT8_ARRAY(data, Flash, 16),
VMSTATE_UINT32(len, Flash),
VMSTATE_UINT32(pos, Flash),
VMSTATE_UINT8(needed_bytes, Flash),
VMSTATE_UINT8(cmd_in_progress, Flash),
VMSTATE_UINT32(cur_addr, Flash),
VMSTATE_BOOL(write_enable, Flash),
VMSTATE_BOOL(reset_enable, Flash),
VMSTATE_UINT8(ear, Flash),
VMSTATE_BOOL(four_bytes_address_mode, Flash),
VMSTATE_UINT32(nonvolatile_cfg, Flash),
VMSTATE_UINT32(volatile_cfg, Flash),
VMSTATE_UINT32(enh_volatile_cfg, Flash),
VMSTATE_BOOL(quad_enable, Flash),
VMSTATE_UINT8(spansion_cr1nv, Flash),
VMSTATE_UINT8(spansion_cr2nv, Flash),
We implement a full 31 packet fifo. */
StellarisEnetRxFrame rx[31];
uint32_t rx_fifo_offset;
uint32_t next_packet;
NICState *nic;
NICConf conf;
qemu_irq irq;
MemoryRegion mmio;
} stellaris_enet_state;
static const VMStateDescription vmstate_rx_frame = {
.name = "stellaris_enet/rx_frame",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048),
VMSTATE_UINT32(len, StellarisEnetRxFrame),
VMSTATE_END_OF_LIST()
}
};
static int stellaris_enet_post_load(void *opaque, int version_id)
{
stellaris_enet_state *s = opaque;
int i;
/* Sanitize inbound state. Note that next_packet is an index but
* np is a size; hence their valid upper bounds differ.
*/
if (s->next_packet >= ARRAY_SIZE(s->rx)) {
return -1;
VMSTATE_INT32(blklen, PXA2xxMMCIState),
VMSTATE_INT32(numblk, PXA2xxMMCIState),
VMSTATE_UINT32(intmask, PXA2xxMMCIState),
VMSTATE_UINT32(intreq, PXA2xxMMCIState),
VMSTATE_INT32(cmd, PXA2xxMMCIState),
VMSTATE_UINT32(arg, PXA2xxMMCIState),
VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
VMSTATE_INT32(active, PXA2xxMMCIState),
VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
VMSTATE_END_OF_LIST()
}
};
#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
#define MMC_STAT 0x04 /* MMC Status register */
#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
#define MMC_SPI 0x0c /* MMC SPI Mode register */
#define MMC_CMDAT 0x10 /* MMC Command/Data register */
#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
#define MMC_BLKLEN 0x1c /* MMC Block Length register */
#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
data->header.flags = SCLP_EVENT_BUFFER_ACCEPTED;
return SCLP_RC_NORMAL_COMPLETION;
}
/* functions for live migration */
static const VMStateDescription vmstate_sclplmconsole = {
.name = "sclplmconsole",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_BOOL(event.event_pending, SCLPConsoleLM),
VMSTATE_UINT32(write_errors, SCLPConsoleLM),
VMSTATE_UINT32(length, SCLPConsoleLM),
VMSTATE_UINT8_ARRAY(buf, SCLPConsoleLM, SIZE_CONSOLE_BUFFER),
VMSTATE_END_OF_LIST()
}
};
/* qemu object creation and initialization functions */
/* tell character layer our call-back functions */
static int console_init(SCLPEvent *event)
{
static bool console_available;
SCLPConsoleLM *scon = SCLPLM_CONSOLE(event);
if (console_available) {
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_gic = {
.name = "arm_gic",
.version_id = 12,
.minimum_version_id = 12,
.pre_save = gic_pre_save,
.post_load = gic_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctlr, GICState),
VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
vmstate_gic_irq_state, gic_irq_state),
VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
VMSTATE_END_OF_LIST()
}
};
void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
return 0;
}
const VMStateDescription vmstate_IPMIBT = {
.name = TYPE_IPMI_INTERFACE_PREFIX "bt",
.version_id = 1,
.minimum_version_id = 1,
.post_load = ipmi_bt_vmstate_post_load,
.fields = (VMStateField[]) {
VMSTATE_BOOL(obf_irq_set, IPMIBT),
VMSTATE_BOOL(atn_irq_set, IPMIBT),
VMSTATE_BOOL(irqs_enabled, IPMIBT),
VMSTATE_UINT32(outpos, IPMIBT),
VMSTATE_UINT32(outlen, IPMIBT),
VMSTATE_UINT8_ARRAY(outmsg, IPMIBT, MAX_IPMI_MSG_SIZE),
VMSTATE_UINT32(inlen, IPMIBT),
VMSTATE_UINT8_ARRAY(inmsg, IPMIBT, MAX_IPMI_MSG_SIZE),
VMSTATE_UINT8(control_reg, IPMIBT),
VMSTATE_UINT8(mask_reg, IPMIBT),
VMSTATE_UINT8(waiting_rsp, IPMIBT),
VMSTATE_UINT8(waiting_seq, IPMIBT),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_ISAIPMIBTDevice = {
.name = TYPE_IPMI_INTERFACE_PREFIX "isa-bt",
.version_id = 2,
.minimum_version_id = 2,
/*
if (written < 0) {
/* event buffer not accepted due to error in character layer */
evt_buf_hdr->flags &= ~(SCLP_EVENT_BUFFER_ACCEPTED);
rc = SCLP_RC_CONTAINED_EQUIPMENT_CHECK;
}
return rc;
}
static const VMStateDescription vmstate_sclpconsole = {
.name = "sclpconsole",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_BOOL(event.event_pending, SCLPConsole),
VMSTATE_UINT8_ARRAY(iov, SCLPConsole, SIZE_BUFFER_VT220),
VMSTATE_UINT32(iov_sclp, SCLPConsole),
VMSTATE_UINT32(iov_bs, SCLPConsole),
VMSTATE_UINT32(iov_data_len, SCLPConsole),
VMSTATE_UINT32(iov_sclp_rest, SCLPConsole),
VMSTATE_END_OF_LIST()
}
};
/* qemu object creation and initialization functions */
/* tell character layer our call-back functions */
static int console_init(SCLPEvent *event)
{
static bool console_available;
.needed = m25p80_data_read_loop_needed,
.fields = (VMStateField[]) {
VMSTATE_BOOL(data_read_loop, Flash),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_m25p80 = {
.name = "m25p80",
.version_id = 0,
.minimum_version_id = 0,
.pre_save = m25p80_pre_save,
.pre_load = m25p80_pre_load,
.fields = (VMStateField[]) {
VMSTATE_UINT8(state, Flash),
VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
VMSTATE_UINT32(len, Flash),
VMSTATE_UINT32(pos, Flash),
VMSTATE_UINT8(needed_bytes, Flash),
VMSTATE_UINT8(cmd_in_progress, Flash),
VMSTATE_UINT32(cur_addr, Flash),
VMSTATE_BOOL(write_enable, Flash),
VMSTATE_BOOL(reset_enable, Flash),
VMSTATE_UINT8(ear, Flash),
VMSTATE_BOOL(four_bytes_address_mode, Flash),
VMSTATE_UINT32(nonvolatile_cfg, Flash),
VMSTATE_UINT32(volatile_cfg, Flash),
VMSTATE_UINT32(enh_volatile_cfg, Flash),
VMSTATE_BOOL(quad_enable, Flash),
VMSTATE_UINT8(spansion_cr1nv, Flash),
VMSTATE_UINT8(spansion_cr2nv, Flash),
VMSTATE_END_OF_LIST()
}
};
static bool riccb_needed(void *opaque)
{
return s390_has_feat(S390_FEAT_RUNTIME_INSTRUMENTATION);
}
const VMStateDescription vmstate_riccb = {
.name = "cpu/riccb",
.version_id = 1,
.minimum_version_id = 1,
.needed = riccb_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(env.riccb, S390CPU, 64),
VMSTATE_END_OF_LIST()
}
};
static bool exval_needed(void *opaque)
{
S390CPU *cpu = opaque;
return cpu->env.ex_value != 0;
}
const VMStateDescription vmstate_exval = {
.name = "cpu/exval",
.version_id = 1,
.minimum_version_id = 1,
.needed = exval_needed,
