/**Function*************************************************************
Synopsis [Performs algebraic balancing of the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Ivy_Man_t * Ivy_ManBalance( Ivy_Man_t * p, int fUpdateLevel )
{
Ivy_Man_t * pNew;
Ivy_Obj_t * pObj, * pDriver;
Vec_Vec_t * vStore;
int i, NewNodeId;
// clean the old manager
Ivy_ManCleanTravId( p );
// create the new manager
pNew = Ivy_ManStart();
// map the nodes
Ivy_ManConst1(p)->TravId = Ivy_EdgeFromNode( Ivy_ManConst1(pNew) );
Ivy_ManForEachPi( p, pObj, i )
pObj->TravId = Ivy_EdgeFromNode( Ivy_ObjCreatePi(pNew) );
// if HAIG is defined, trasfer the pointers to the PIs/latches
// if ( p->pHaig )
// Ivy_ManHaigTrasfer( p, pNew );
// balance the AIG
vStore = Vec_VecAlloc( 50 );
Ivy_ManForEachPo( p, pObj, i )
{
pDriver = Ivy_ObjReal( Ivy_ObjChild0(pObj) );
NewNodeId = Ivy_NodeBalance_rec( pNew, Ivy_Regular(pDriver), vStore, 0, fUpdateLevel );
NewNodeId = Ivy_EdgeNotCond( NewNodeId, Ivy_IsComplement(pDriver) );
Ivy_ObjCreatePo( pNew, Ivy_EdgeToNode(pNew, NewNodeId) );
}
/**Function*************************************************************
Synopsis [Write one network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_NtkWriteEqnOne( FILE * pFile, Abc_Ntk_t * pNtk )
{
Vec_Vec_t * vLevels;
ProgressBar * pProgress;
Abc_Obj_t * pNode, * pFanin;
int i, k;
// write the PIs
fprintf( pFile, "INORDER =" );
Io_NtkWriteEqnCis( pFile, pNtk );
fprintf( pFile, ";\n" );
// write the POs
fprintf( pFile, "OUTORDER =" );
Io_NtkWriteEqnCos( pFile, pNtk );
fprintf( pFile, ";\n" );
// write each internal node
vLevels = Vec_VecAlloc( 10 );
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
fprintf( pFile, "%s = ", Abc_ObjName(Abc_ObjFanout0(pNode)) );
// set the input names
Abc_ObjForEachFanin( pNode, pFanin, k )
Hop_IthVar((Hop_Man_t *)pNtk->pManFunc, k)->pData = Abc_ObjName(pFanin);
// write the formula
Hop_ObjPrintEqn( pFile, (Hop_Obj_t *)pNode->pData, vLevels, 0 );
fprintf( pFile, ";\n" );
}
/**Function*************************************************************
Synopsis [Returns the nodes by level.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Vec_t * Ivy_ManLevelize( Ivy_Man_t * p )
{
Vec_Vec_t * vNodes;
Ivy_Obj_t * pObj;
int i;
vNodes = Vec_VecAlloc( 100 );
Ivy_ManForEachObj( p, pObj, i )
{
assert( !Ivy_ObjIsBuf(pObj) );
if ( Ivy_ObjIsNode(pObj) )
Vec_VecPush( vNodes, pObj->Level, pObj );
}
/**Function*************************************************************
Synopsis [Computes the retiming lags for FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Seq_FpgaMappingDelays( Abc_Ntk_t * pNtk, int fVerbose )
{
Abc_Seq_t * p = pNtk->pManFunc;
Cut_Params_t Params, * pParams = &Params;
Abc_Obj_t * pObj;
int i, clk;
// set defaults for cut computation
memset( pParams, 0, sizeof(Cut_Params_t) );
pParams->nVarsMax = p->nVarsMax; // the max cut size ("k" of the k-feasible cuts)
pParams->nKeepMax = 1000; // the max number of cuts kept at a node
pParams->fTruth = 0; // compute truth tables
pParams->fFilter = 1; // filter dominated cuts
pParams->fSeq = 1; // compute sequential cuts
pParams->fVerbose = fVerbose; // the verbosiness flag
// compute the cuts
clk = clock();
p->pCutMan = Abc_NtkSeqCuts( pNtk, pParams );
// pParams->fSeq = 0;
// p->pCutMan = Abc_NtkCuts( pNtk, pParams );
p->timeCuts = clock() - clk;
if ( fVerbose )
Cut_ManPrintStats( p->pCutMan );
// compute area flows
// Seq_MapComputeAreaFlows( pNtk, fVerbose );
// compute the delays
clk = clock();
if ( !Seq_AigRetimeDelayLags( pNtk, fVerbose ) )
return 0;
p->timeDelay = clock() - clk;
// collect the nodes and cuts used in the mapping
p->vMapAnds = Vec_PtrAlloc( 1000 );
p->vMapCuts = Vec_VecAlloc( 1000 );
Abc_NtkIncrementTravId( pNtk );
Abc_NtkForEachPo( pNtk, pObj, i )
Seq_FpgaMappingCollectNode_rec( Abc_ObjFanin0(pObj), p->vMapAnds, p->vMapCuts );
if ( fVerbose )
printf( "The number of LUTs = %d.\n", Vec_PtrSize(p->vMapAnds) );
// remove the cuts
Cut_ManStop( p->pCutMan );
p->pCutMan = NULL;
return 1;
}
