/*-----------------------------------------------------------------------------
* Function: hdcp_lib_generate_an
*-----------------------------------------------------------------------------
*/
static void hdcp_lib_generate_an(u8 *an)
{
/* Generate An using HDCP HW */
DBG("hdcp_lib_generate_an()");
/* Start AN Gen */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 3, 3, 0);
/* Delay of 10 ms */
mdelay(10);
/* Stop AN Gen */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 3, 3, 1);
/* Must set 0x72:0x0F[3] twice to guarantee that takes effect */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 3, 3, 1);
hdcp_lib_read_an(an);
DBG("AN: %x %x %x %x %x %x %x %x", an[0], an[1], an[2], an[3],
an[4], an[5], an[6], an[7]);
}
/*-----------------------------------------------------------------------------
* Function: hdcp_lib_auto_ri_check
*-----------------------------------------------------------------------------
*/
void hdcp_lib_auto_ri_check(bool state)
{
u8 reg_val;
unsigned long flags;
DBG("hdcp_lib_auto_ri_check() state=%s",
state == true ? "ON" : "OFF");
spin_lock_irqsave(&hdcp.spinlock, flags);
reg_val = RD_REG_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__INT_UNMASK3);
reg_val = (state == true) ? (reg_val | 0xB0) : (reg_val & ~0xB0);
/* Turn on/off the following Auto Ri interrupts */
WR_REG_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__INT_UNMASK3, reg_val);
/* Enable/Disable Ri */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__RI_CMD, 0, 0,
((state == true) ? 1 : 0));
/* Read to flush */
RD_REG_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__RI_CMD);
spin_unlock_irqrestore(&hdcp.spinlock, flags);
}
/*-----------------------------------------------------------------------------
* Function: hdcp_lib_auto_bcaps_rdy_check
*-----------------------------------------------------------------------------
*/
void hdcp_lib_auto_bcaps_rdy_check(bool state)
{
u8 reg_val;
unsigned long flags;
DBG("hdcp_lib_auto_bcaps_rdy_check() state=%s",
state == true ? "ON" : "OFF");
spin_lock_irqsave(&hdcp.spinlock, flags);
/* Enable KSV_READY / BACP_DONE interrupt */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__INT_UNMASK2, 7, 7,
((state == true) ? 1 : 0));
/* Enable/Disable Ri & Bcap */
reg_val = RD_REG_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__RI_CMD);
/* Enable RI_EN & BCAP_EN OR disable BCAP_EN */
reg_val = (state == true) ? (reg_val | 0x3) : (reg_val & ~0x2);
WR_REG_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__RI_CMD, reg_val);
/* Read to flush */
RD_REG_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__RI_CMD);
spin_unlock_irqrestore(&hdcp.spinlock, flags);
DBG("hdcp_lib_auto_bcaps_rdy_check() Done\n");
}
/*-----------------------------------------------------------------------------
* Function: hdcp_lib_set_repeater_bit_in_tx
*-----------------------------------------------------------------------------
*/
static void hdcp_lib_set_repeater_bit_in_tx(enum hdcp_repeater rx_mode)
{
DBG("hdcp_lib_set_repeater_bit_in_tx() value=%d", rx_mode);
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 4, 4, rx_mode);
}
/*-----------------------------------------------------------------------------
* Function: hdcp_3des_encrypt_key
*-----------------------------------------------------------------------------
*/
void hdcp_3des_encrypt_key(struct hdcp_encrypt_control *enc_ctrl,
uint32_t out_key[DESHDCP_KEY_SIZE])
{
int counter = 0;
DBG("Encrypting HDCP keys...");
/* Reset encrypted key array */
for (counter = 0; counter < DESHDCP_KEY_SIZE; counter++)
out_key[counter] = 0;
/* Set encryption mode in DES control register */
WR_FIELD_32(hdcp.deshdcp_base_addr,
DESHDCP__DHDCP_CTRL,
DESHDCP__DHDCP_CTRL__DIRECTION_POS_F,
DESHDCP__DHDCP_CTRL__DIRECTION_POS_L,
0x1);
/* Write raw data and read encrypted data */
counter = 0;
#ifdef POWER_TRANSITION_DBG
printk(KERN_ERR "\n**************************\n"
"ENCRYPTION: WAIT FOR DSS TRANSITION\n"
"*************************\n");
mdelay(10000);
printk(KER_INFO "\n**************************\n"
"DONE\n"
"*************************\n");
#endif
while (counter < DESHDCP_KEY_SIZE) {
/* Fill Data registers */
WR_REG_32(hdcp.deshdcp_base_addr, DESHDCP__DHDCP_DATA_L,
enc_ctrl->in_key[counter]);
WR_REG_32(hdcp.deshdcp_base_addr, DESHDCP__DHDCP_DATA_H,
enc_ctrl->in_key[counter + 1]);
/* Wait for output bit at '1' */
while (RD_FIELD_32(hdcp.deshdcp_base_addr,
DESHDCP__DHDCP_CTRL,
DESHDCP__DHDCP_CTRL__OUTPUT_READY_POS_F,
DESHDCP__DHDCP_CTRL__OUTPUT_READY_POS_L
) != 0x1)
;
/* Read enrypted data */
out_key[counter] = RD_REG_32(hdcp.deshdcp_base_addr,
DESHDCP__DHDCP_DATA_L);
out_key[counter + 1] = RD_REG_32(hdcp.deshdcp_base_addr,
DESHDCP__DHDCP_DATA_H);
counter += 2;
}
}
int hdcp_3des_load_key(uint32_t *deshdcp_encrypted_key)
{
int counter = 0, status = HDCP_OK;
if (!deshdcp_encrypted_key) {
HDCP_ERR("HDCP keys NULL, failed to load keys\n");
return HDCP_3DES_ERROR;
}
HDCP_DBG("Loading HDCP keys...\n");
/* Set decryption mode in DES control register */
WR_FIELD_32(hdcp.deshdcp_base_addr,
DESHDCP__DHDCP_CTRL,
DESHDCP__DHDCP_CTRL__DIRECTION_POS_F,
DESHDCP__DHDCP_CTRL__DIRECTION_POS_L,
0x0);
/* Write encrypted data */
while (counter < DESHDCP_KEY_SIZE) {
/* Fill Data registers */
WR_REG_32(hdcp.deshdcp_base_addr, DESHDCP__DHDCP_DATA_L,
deshdcp_encrypted_key[counter]);
WR_REG_32(hdcp.deshdcp_base_addr, DESHDCP__DHDCP_DATA_H,
deshdcp_encrypted_key[counter + 1]);
/* Wait for output bit at '1' */
while (RD_FIELD_32(hdcp.deshdcp_base_addr,
DESHDCP__DHDCP_CTRL,
DESHDCP__DHDCP_CTRL__OUTPUT_READY_POS_F,
DESHDCP__DHDCP_CTRL__OUTPUT_READY_POS_L) != 0x1)
;
/* Dummy read (indeed data are transfered directly into
* key memory)
*/
if (RD_REG_32(hdcp.deshdcp_base_addr, DESHDCP__DHDCP_DATA_L)
!= 0x0) {
status = -HDCP_3DES_ERROR;
HDCP_ERR("DESHDCP dummy read error\n");
}
if (RD_REG_32(hdcp.deshdcp_base_addr, DESHDCP__DHDCP_DATA_H) !=
0x0) {
status = -HDCP_3DES_ERROR;
HDCP_ERR("DESHDCP dummy read error\n");
}
counter += 2;
}
if (status == HDCP_OK)
hdcp.hdcp_keys_loaded = true;
return status;
}
/*-----------------------------------------------------------------------------
* Function: hdcp_lib_disable
*-----------------------------------------------------------------------------
*/
int hdcp_lib_disable()
{
DBG("hdcp_lib_disable() %u", jiffies_to_msecs(jiffies));
/* CP reset */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 2, 2, 0);
/* Clear AV mute in case it was set */
hdcp_lib_set_av_mute(AV_MUTE_CLEAR);
return HDCP_OK;
}
/*-----------------------------------------------------------------------------
* Function: hdcp_lib_set_av_mute
*-----------------------------------------------------------------------------
*/
void hdcp_lib_set_av_mute(enum av_mute av_mute_state)
{
unsigned long flags;
DBG("hdcp_lib_set_av_mute() av_mute=%d", av_mute_state);
spin_lock_irqsave(&hdcp.spinlock, flags);
{
u8 RegVal, TimeOutCount = 64;
RegVal = RD_REG_32(hdcp.hdmi_wp_base_addr + HDMI_CORE_AV_BASE,
HDMI_CORE_AV_PB_CTRL2);
/* PRguide-GPC: To change the content of the CP_BYTE1 register,
* CP_EN must be zero
* set PB_CTRL2 :: CP_RPT = 0
*/
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_CORE_AV_BASE,
HDMI_CORE_AV_PB_CTRL2, 2, 2, 0);
/* Set/clear AV mute state */
WR_REG_32(hdcp.hdmi_wp_base_addr + HDMI_CORE_AV_BASE,
HDMI_CORE_AV_CP_BYTE1, av_mute_state);
/* FIXME: This loop should be removed */
while (TimeOutCount--) {
/* Continue in this loop till CP_EN becomes 0,
* prior to TimeOutCount becoming 0 */
if (!RD_FIELD_32(hdcp.hdmi_wp_base_addr +
HDMI_CORE_AV_BASE,
HDMI_CORE_AV_PB_CTRL2, 3, 3))
break;
}
DBG(" timeoutcount=%d", TimeOutCount);
/* FIXME: why is this if condition required?, according to prg,
* this shall be unconditioanlly */
if (TimeOutCount) {
/* set PB_CTRL2 :: CP_EN = 1 & CP_RPT = 1 */
RegVal = FLD_MOD(RegVal, 0x3, 3, 2);
WR_REG_32(hdcp.hdmi_wp_base_addr + HDMI_CORE_AV_BASE,
HDMI_CORE_AV_PB_CTRL2, RegVal);
}
}
spin_unlock_irqrestore(&hdcp.spinlock, flags);
}
/*-----------------------------------------------------------------------------
* Function: hdcp_lib_set_encryption
*-----------------------------------------------------------------------------
*/
void hdcp_lib_set_encryption(enum encryption_state enc_state)
{
unsigned long flags;
spin_lock_irqsave(&hdcp.spinlock, flags);
/* HDCP_CTRL::ENC_EN set/clear */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 0, 0, enc_state);
/* Read to flush */
RD_REG_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL);
spin_unlock_irqrestore(&hdcp.spinlock, flags);
pr_info("HDCP: Encryption state changed: %s hdcp_ctrl: %02x",
enc_state == HDCP_ENC_OFF ? "OFF" : "ON",
RD_REG_32(hdcp.hdmi_wp_base_addr +
HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL));
}
/*-----------------------------------------------------------------------------
* Function: hdcp_lib_initiate_step1
*-----------------------------------------------------------------------------
*/
static int hdcp_lib_initiate_step1(void)
{
/* HDCP authentication steps:
* 1) Read Bksv - check validity (is HDMI Rx supporting HDCP ?)
* 2) Initializes HDCP (CP reset release)
* 3) Read Bcaps - is HDMI Rx a repeater ?
* *** First part authentication ***
* 4) Read Bksv - check validity (is HDMI Rx supporting HDCP ?)
* 5) Generates An
* 6) DDC: Writes An, Aksv
* 7) DDC: Write Bksv
*/
uint8_t an_ksv_data[8], an_bksv_data[8];
uint8_t rx_type;
DBG("hdcp_lib_initiate_step1()\n");
/* DDC: Read BKSV from RX */
if (hdcp_ddc_read(DDC_BKSV_LEN, DDC_BKSV_ADDR , an_ksv_data))
return -HDCP_DDC_ERROR;
if (hdcp.pending_disable)
return -HDCP_CANCELLED_AUTH;
DBG("BKSV: %02x %02x %02x %02x %02x", an_ksv_data[0], an_ksv_data[1],
an_ksv_data[2], an_ksv_data[3],
an_ksv_data[4]);
if (hdcp_lib_check_ksv(an_ksv_data)) {
DBG("BKSV error (number of 0 and 1)");
return -HDCP_AUTH_FAILURE;
}
/* TODO: Need to confirm it is required */
#ifndef _9032_AN_STOP_FIX_
hdcp_lib_toggle_repeater_bit_in_tx();
#endif
/* Release CP reset bit */
WR_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 2, 2, 1);
/* Read BCAPS to determine if HDCP RX is a repeater */
if (hdcp_ddc_read(DDC_BCAPS_LEN, DDC_BCAPS_ADDR, &rx_type))
return -HDCP_DDC_ERROR;
if (hdcp.pending_disable)
return -HDCP_CANCELLED_AUTH;
rx_type = FLD_GET(rx_type, DDC_BIT_REPEATER, DDC_BIT_REPEATER);
/* Set repeater bit in HDCP CTRL */
if (rx_type == 1) {
hdcp_lib_set_repeater_bit_in_tx(HDCP_REPEATER);
DBG("HDCP RX is a repeater");
} else {
hdcp_lib_set_repeater_bit_in_tx(HDCP_RECEIVER);
DBG("HDCP RX is a receiver");
}
/* Power debug code */
#ifdef POWER_TRANSITION_DBG
printk(KERN_INFO "\n**************************\n"
"AUTHENTICATION: WAIT FOR DSS TRANSITION\n"
"*************************\n");
mdelay(10000);
printk(KERN_INFO "\n**************************\n"
"DONE\n"
"*************************\n");
#endif
/* DDC: Read BKSV from RX */
if (hdcp_ddc_read(DDC_BKSV_LEN, DDC_BKSV_ADDR , an_bksv_data))
return -HDCP_DDC_ERROR;
/* Generate An */
hdcp_lib_generate_an(an_ksv_data);
/* Authentication 1st step initiated HERE */
/* DDC: Write An */
if (hdcp_ddc_write(DDC_AN_LEN, DDC_AN_ADDR , an_ksv_data))
return -HDCP_DDC_ERROR;
if (hdcp.pending_disable)
return -HDCP_CANCELLED_AUTH;
/* Read AKSV from IP: (HDCP AKSV register) */
hdcp_lib_read_aksv(an_ksv_data);
DBG("AKSV: %02x %02x %02x %02x %02x", an_ksv_data[0], an_ksv_data[1],
an_ksv_data[2], an_ksv_data[3],
an_ksv_data[4]);
if (hdcp_lib_check_ksv(an_ksv_data)) {
printk(KERN_INFO "HDCP: AKSV error (number of 0 and 1)\n");
return -HDCP_AKSV_ERROR;
}
if (hdcp.pending_disable)
return -HDCP_CANCELLED_AUTH;
/* DDC: Write AKSV */
if (hdcp_ddc_write(DDC_AKSV_LEN, DDC_AKSV_ADDR, an_ksv_data))
return -HDCP_DDC_ERROR;
if (hdcp.pending_disable)
return -HDCP_CANCELLED_AUTH;
/* Write Bksv to IP */
hdcp_lib_write_bksv(an_bksv_data);
/* Check IP BKSV error */
if (RD_FIELD_32(hdcp.hdmi_wp_base_addr + HDMI_IP_CORE_SYSTEM,
HDMI_IP_CORE_SYSTEM__HDCP_CTRL, 5, 5))
return -HDCP_AUTH_FAILURE;
/* Here BSKV should be checked against revokation list */
return HDCP_OK;
}
