/*
* The function is local to Flash app
* used to write the block of data
*/
void FLASH003_lWriteBlock (uint32_t Address, const uint32_t pBuf[])
{
uint32_t lWord_Cnt;
const FLASH003_HandleType* Handle;
Handle = &FLASH003_Handle0;
/*updating the ACTION with Oneshot Write and Auto Verify*/
WR_REG(Handle->FlashRegsPtr->NVMPROG,NVM_NVMPROG_ACTION_Msk,\
NVM_NVMPROG_ACTION_Pos,FLASH003_ONESHOT_WRITE_AUTOVERIFY);
/*Writing a Block of Data*/
for(lWord_Cnt = 0U;lWord_Cnt < FLASH003_WORD_SIZE;lWord_Cnt++)
{
*((uint32_t *) (Address + (FLASH003_WORD_SIZE * lWord_Cnt) )) = \
pBuf[lWord_Cnt];
}
#if (FLASH003_SEQ_INTERRUPT != FLASH003_INTR_ENABLED)
/*Polling Busy Flag until Idle State*/
while(RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_BUSY_Msk,\
NVM_NVMSTATUS_BUSY_Pos) != FLASH003_RESET)
{
;
}
/*Wait for 10us to complete the verification(need to check)*/
WR_REG(SCU_CLK->CLKCR, SCU_CLK_CLKCR_CNTADJ_Msk, SCU_CLK_CLKCR_CNTADJ_Pos,\
FLASH003_DELAY);
while (SCU_CLK->CLKCR&(SCU_CLK_CLKCR_VDDC2LOW_Msk))
{
;
}
#endif
}
void DAVE_MUX_PreInit(void)
{
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT14->PDISC, PORT14_PDISC_PDIS6_Msk, PORT14_PDISC_PDIS6_Pos, PORT_PDISC_PDIS0); /* P14.6 : PORT14_PDISC_PDIS6 */
WR_REG(PORT14->PDISC, PORT14_PDISC_PDIS7_Msk, PORT14_PDISC_PDIS7_Pos, PORT_PDISC_PDIS0); /* P14.7 : PORT14_PDISC_PDIS7 */
}
/**
* This function allows user to change the functionality
* for the given external event.
*/
status_t PWMSP003_RemapEvent(const PWMSP003_HandleType * HandlePtr,
PWMSP003_ExtEventType ExtEvent,
PWMSP003_ExtEventFunctionType Function)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if (HandlePtr->DynamicDataType->StateType != PWMSP003_RUNNING)
{
/* Trap can be configured only for event 2 */
if(((uint32_t)ExtEvent == PWMSP003_EVENT_2) &&
((uint32_t)Function == PWMSP003_EXTERNAL_TRAP))
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC, (uint32_t)CCU4_CC4_CMC_TS_Msk,\
(uint32_t)CCU4_CC4_CMC_TS_Pos, PWMSP003_EVENT_2);
Status = (uint32_t)DAVEApp_SUCCESS;
}
else if(((uint32_t)ExtEvent!=PWMSP003_EVENT_2) &&
((uint32_t)Function==PWMSP003_EXTERNAL_TRAP))
{
Status = PWMSP003_INVALID_PARAM_ERROR;
}
/* Override can be configured only for event 1 and event 2 */
else if(((ExtEvent == PWMSP003_EVENT_1)
|| ((uint32_t)ExtEvent == PWMSP003_EVENT_2))
&& ((uint32_t)Function == PWMSP003_EXTERNAL_OVERRIDE))
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC, (uint32_t)CCU4_CC4_CMC_OFS_Msk,\
(uint32_t)CCU4_CC4_CMC_OFS_Pos, (uint32_t)ExtEvent);
Status = (uint32_t)DAVEApp_SUCCESS;
}
else if(((uint32_t)ExtEvent == PWMSP003_EVENT_0) &&\
((uint32_t)Function == PWMSP003_EXTERNAL_OVERRIDE))
{
Status = PWMSP003_INVALID_PARAM_ERROR;
}
else
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC,\
((uint32_t)CCU4_CC4_CMC_STRTS_Msk << (uint32_t)Function),\
((uint32_t)CCU4_CC4_CMC_STRTS_Pos + (uint32_t)Function),\
(uint32_t)ExtEvent);
Status = (uint32_t)DAVEApp_SUCCESS;
}
}
return Status;
}
/*******************************************************************************
* @brief This function initialises the App, based on User provided
* configuration.
*
* @param[in] None
*
* @return None <BR>
*
* <b>Reentrant: No </b><BR>
******************************************************************************/
void I2C003_Init(void)
{
uint32_t LoopIndex;
#if (__TARGET_DEVICE__ != XMC45)
#if ((__TARGET_DEVICE__ == XMC13) || \
(__TARGET_DEVICE__ == XMC12) || \
(__TARGET_DEVICE__ == XMC11))
/* Disable the USIC0/USIC1 clock gating for XMC1000 devices */
SCU_GENERAL->PASSWD = 0x000000C0UL;
WR_REG(SCU_CLK->CLKCR, SCU_CLK_CLKCR_CNTADJ_Msk, \
SCU_CLK_CLKCR_CNTADJ_Pos,CLK002_DELAYCNT);
#if defined(I2C003_PER0_USIC0_ENABLED)
SET_BIT(SCU_CLK->CGATCLR0, SCU_CLK_CGATCLR0_USIC0_Pos);
#endif
#if defined(I2C003_PER1_USIC1_ENABLED)
SET_BIT(SCU_CLK->CGATCLR1, SCU_CLK_CGATCLR1_USIC1_Pos);
#endif
while ((SCU_CLK->CLKCR)&(SCU_CLK_CLKCR_VDDC2LOW_Msk))
{
;
}
SCU_GENERAL->PASSWD = 0x000000C3UL;
#else
/* Disable the USIC0/USIC1 clock gating for XMC4400 and XMC4200 devices*/
#if defined(I2C003_PER0_USIC0_ENABLED)
SET_BIT(SCU_CLK->CGATCLR0, SCU_CLK_CGATCLR0_USIC0_Pos);
#endif
#if defined(I2C003_PER1_USIC1_ENABLED)
SET_BIT(SCU_CLK->CGATCLR1, SCU_CLK_CGATCLR1_USIC1_Pos);
#endif
#endif
#endif
#if ((__TARGET_DEVICE__ == XMC45) || \
(__TARGET_DEVICE__ == XMC44) || \
(__TARGET_DEVICE__ == XMC42))
/* Reset the Peripheral*/
#if defined(I2C003_PER0_USIC0_ENABLED)
RESET001_DeassertReset(PER0_USIC0);
#endif
#if defined(I2C003_PER1_USIC1_ENABLED)
RESET001_DeassertReset(PER1_USIC1);
#endif
#if defined(I2C003_PER1_USIC2_ENABLED)
RESET001_DeassertReset(PER1_USIC2);
#endif
#endif
for (LoopIndex = (uint32_t)0; LoopIndex < (uint32_t)I2C003_NUM_HANDLES; \
LoopIndex++)
{
I2C003_lConfigSCLPin(I2C003_HandleArray[LoopIndex]);
I2C003_lConfigSDAPin(I2C003_HandleArray[LoopIndex]);
I2C003_lInit(I2C003_HandleArray[LoopIndex]);
}
}
void DAVE_MUX_PreInit(void)
{
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT2->PDISC, PORT2_PDISC_PDIS0_Msk, PORT2_PDISC_PDIS0_Pos, PORT_PDISC_PDIS0); /* P2.0 : PORT2_PDISC_PDIS0 */
}
/**
* This function starts the app.
* This function should be called even if external start is configured.
*/
status_t PWMSP003_Start(const PWMSP003_HandleType* HandlePtr)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
do
{
if((HandlePtr->DynamicDataType->StateType == PWMSP003_UNINITIALIZED) ||
(HandlePtr->DynamicDataType->StateType == PWMSP003_RUNNING))
{
break;
}
HandlePtr->CC4yRegsPtr->SWR = PWMSP003_ALL_CCU4_INTR_CLEAR;
/* Start the Prescaler */
HandlePtr->CC4yKernRegsPtr->GIDLC |=\
((uint32_t)0x1U << ((uint32_t)CCU4_GIDLC_SPRB_Pos));
/* Start the timer slice */
HandlePtr->CC4yKernRegsPtr->GIDLC |=\
((uint32_t)0x1U << ((uint32_t)CCU4_GIDLC_CS0I_Pos +\
(uint32_t)HandlePtr->Slice));
WR_REG(HandlePtr->CC4yRegsPtr->TC, CCU4_CC4_TC_TRAPE_Msk,\
(uint32_t)CCU4_CC4_TC_TRAPE_Pos, HandlePtr->kTrapEnable);
/* Set run bit of slices if external start is not configured */
if (HandlePtr->kStartEvent == PWMSP003_NO_EVENT)
{
HandlePtr->CC4yRegsPtr->TCSET |= (uint32_t)0x1U;
}
else
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC,\
(uint32_t)CCU4_CC4_CMC_STRTS_Msk,\
(uint32_t)CCU4_CC4_CMC_STRTS_Pos,\
HandlePtr->kStartEvent);
}
HandlePtr->DynamicDataType->StateType = PWMSP003_RUNNING;
Status = (uint32_t)DAVEApp_SUCCESS;
} while (0);
return Status;
}
void alpha8201_cpu_device::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
case ALPHA8201_PC:
m_PREVPC = m_pc.w.l;
break;
case STATE_GENPCBASE:
m_pc.w.l = m_PREVPC;
break;
case STATE_GENFLAGS:
m_cf = BIT(m_flags, 1);
m_zf = BIT(m_flags, 0);
break;
case ALPHA8201_SP:
case STATE_GENSP:
M_WRMEM(0x001, m_sp);
break;
case ALPHA8201_R0:
WR_REG(0, m_R[0]);
break;
case ALPHA8201_R1:
WR_REG(1, m_R[1]);
break;
case ALPHA8201_R2:
WR_REG(2, m_R[2]);
break;
case ALPHA8201_R3:
WR_REG(3, m_R[3]);
break;
case ALPHA8201_R4:
WR_REG(4, m_R[4]);
break;
case ALPHA8201_R5:
WR_REG(5, m_R[5]);
break;
case ALPHA8201_R6:
WR_REG(6, m_R[6]);
break;
case ALPHA8201_R7:
WR_REG(7, m_R[7]);
break;
}
}
void clearErrorFlags(void)
{
if(USIC1_CH1->PSR_IICMode & (USIC_CH_PSR_IICMode_ERR_Msk | USIC_CH_PSR_IICMode_NACK_Msk))
{
// Clear error bits
USIC1_CH1->PSCR |= 0x3FF;
// Flush transmit FIFO buffer
USIC1_CH1->TRBSCR |= USIC_CH_TRBSCR_FLUSHTB_Msk;
// Modify Transmit Data Valid
WR_REG(USIC1_CH1->FMR, USIC_CH_FMR_MTDV_Msk, USIC_CH_FMR_MTDV_Pos, 2);
}
}
/**
* This function clear the requested event flag for the given slice
*/
status_t PWMSP003_AcknowledgeInterrupt(const PWMSP003_HandleType * HandlePtr,
PWMSP003_InterruptType Event)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if (HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
WR_REG(HandlePtr->CC4yRegsPtr->SWR,\
(CCU4_CC4_SWR_RPM_Msk << (uint32_t)Event),\
(CCU4_CC4_SWR_RPM_Pos + (uint32_t)Event),\
(uint32_t)0x1U);
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
static void CCU4Global_lInit(const CCU4Global_HandleType * Handle)
{
if( Handle->KernelNumber <= 2 )
{
/* Disables the gating for CCU4 kernel */
/*This is applicable for XMC4400,XMC4200 and XMC1xxx Devices*/
#if (UC_FAMILY == XMC1 )
if (!((uint32_t)SCU_CLK->CGATCLR0 & Handle->ClockGating))
{
SCU_GENERAL->PASSWD = 0x000000C0UL;
WR_REG(SCU_CLK->CLKCR, SCU_CLK_CLKCR_CNTADJ_Msk,
SCU_CLK_CLKCR_CNTADJ_Pos,CCU4GLOBAL_DELAYCNT);
SET_BIT(SCU_CLK->CGATCLR0, Handle->ClockGating);
while ((uint32_t)SCU_CLK->CLKCR &
(uint32_t)SCU_CLK_CLKCR_VDDC2LOW_Msk)
{
;
}
SCU_GENERAL->PASSWD = 0x000000C3UL;
}
#endif
#if ((__TARGET_DEVICE__ == XMC42) || (__TARGET_DEVICE__ == XMC44))
SET_BIT(SCU_CLK->CGATCLR0, Handle->ClockGating);
#endif
}
#if (__TARGET_DEVICE__ == XMC44)
else
{
SET_BIT(SCU_CLK->CGATCLR1, Handle->ClockGating);
}
#endif
#if (UC_FAMILY == XMC4)
/* Deassert the peripheral */
/*This is applicable for XMC4500, XMC4400 and XMC4200 Devices*/
RESET001_DeassertReset(Handle->PeripheralReset);
#endif
/* Sets Run bit of the Prescalar */
SET_BIT(Handle->CC4yKernRegsPtr->GIDLC,CCU4_GIDLC_SPRB_Pos);
}
void alpha8201_cpu_device::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
case ALPHA8201_SP:
M_WRMEM(0x001, m_sp);
break;
case ALPHA8201_R0:
WR_REG(0, m_R[0]);
break;
case ALPHA8201_R1:
WR_REG(1, m_R[1]);
break;
case ALPHA8201_R2:
WR_REG(2, m_R[2]);
break;
case ALPHA8201_R3:
WR_REG(3, m_R[3]);
break;
case ALPHA8201_R4:
WR_REG(4, m_R[4]);
break;
case ALPHA8201_R5:
WR_REG(5, m_R[5]);
break;
case ALPHA8201_R6:
WR_REG(6, m_R[6]);
break;
case ALPHA8201_R7:
WR_REG(7, m_R[7]);
break;
}
}
/**
* This function allows user to change the input mapping
* for the given event.
*/
status_t PWMSP003_RemapInput(const PWMSP003_HandleType * HandlePtr,
PWMSP003_InputSelectionType Input,
PWMSP003_ExtEventType ExtEvent)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if ((HandlePtr->DynamicDataType->StateType != PWMSP003_RUNNING))
{
WR_REG(HandlePtr->CC4yRegsPtr->INS,\
((uint32_t)CCU4_CC4_INS_EV0IS_Msk <<\
(uint32_t)(((uint32_t)ExtEvent - 1U) * PWMSP003_NO_OF_SLICES)),\
((uint32_t)CCU4_CC4_INS_EV0IS_Pos +\
(uint32_t)(((uint32_t)ExtEvent - 1U) * PWMSP003_NO_OF_SLICES)),\
(uint32_t)Input);
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
/******************************************************************************
** Public Function Definitions **
******************************************************************************/
void UART001_Init(void)
{
/* Disable the USIC0 clock gating */
/*
* The disabling of the clock gating is applicable only for
* XMC4400, XMC4200 and XMC1000 devices.
*/
SCU_GENERAL->PASSWD = 0x000000C0UL;
WR_REG(SCU_CLK->CLKCR, SCU_CLK_CLKCR_CNTADJ_Msk, \
SCU_CLK_CLKCR_CNTADJ_Pos,CLK002_DELAYCNT);
SET_BIT(SCU_CLK->CGATCLR0, SCU_CLK_CGATCLR0_USIC0_Pos);
while ((SCU_CLK->CLKCR)&(SCU_CLK_CLKCR_VDDC2LOW_Msk))
{
;
}
SCU_GENERAL->PASSWD = 0x000000C3UL;
UART001_lInit(&UART001_Handle0);
/* Configuration of TX Pin 1.3 based on User configuration */
/* Configuration of RX Pin 1.2 based on User configuration */
}
/* This Function sets the event Count Match. This is the compare register value of the CCU4x_CCy slice */
status_t CNT001_SetCountMatch(const CNT001_HandleType *HandlePtr, uint32_t CountMatch)
{
status_t status = (uint32_t)CNT001_OPER_NOT_ALLOWED_ERROR;
CCU4_CC4_TypeDef *CCU4Ptr; /* Pointer to the CCU4 Register set */
CCU4_GLOBAL_TypeDef *CCU4KernelPtr; /* Pointer to the CCU4 Kernel Register set */
CCU4Ptr = HandlePtr->CC4Ptr;
CCU4KernelPtr = HandlePtr->CC4KernalPtr;
DBG002_FUNCTION_ENTRY(APP_GID, (uint32_t)CNT001_FUNCTION_ENTRY);
/*<<<DD_CNT001_API_7_1>>>*/
if (HandlePtr->DynamicHandlePtr->State != CNT001_INITIALIZED)
{
DBG002_INFO(APP_GID, DBG002_MESSAGEID_LITERAL, CNT001_STATUS_LEN, &status);
}
else if( CountMatch > CNT001_EVENT_COUNT_MAX )
{
status = (uint32_t)CNT001_OUT_OF_RANGE_ERROR;
}
else
{
/*<<<DD_CNT001_API_7_5>>>*/
/* Update the Count match value in CRS Register */
WR_REG(CCU4Ptr->CRS, (uint32_t)CCU4_CC4_CRS_CRS_Msk, \
(uint32_t)CCU4_CC4_CRS_CRS_Pos,CountMatch);
/* Request SW Shadow Transfer */
CCU4KernelPtr->GCSS |=
(uint32_t)((0x01UL << ((uint32_t)4 * (uint32_t)HandlePtr->CCUInUse)));
/* Update the Dynamic HandlePtr */
HandlePtr->DynamicHandlePtr ->NewCountMatch = CountMatch;
status = (uint32_t)DAVEApp_SUCCESS;
}
DBG002_FUNCTION_EXIT(APP_GID, (uint32_t)CNT001_FUNCTION_EXIT);
return status;
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[2] |= (uint32_t) RD_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[4] |= (uint32_t) RD_REG(USIC2_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC2_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC1_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x06000000); /* DPTR = 0, SIZE = 6 */
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC2_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC2_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x01000008); /* DPTR = 8, SIZE = 1 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC2_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x03000000); /* DPTR = 0, SIZE = 3 */
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[2]);
WR_REG(USIC2_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[4]);
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT0->IOCR4, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P0.5 : PORT0_IOCR4_PC5_PCR and PORT0_IOCR4_PC5_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P1.0 : PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P1.1 : PORT1_IOCR0_PC1_OE */
WR_REG(PORT5->IOCR0, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x11U); /*P5.0 : PORT5_IOCR0_PC0_PCR and PORT5_IOCR0_PC0_OE */
WR_REG(PORT5->IOCR0, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x11U); /*P5.2 : PORT5_IOCR0_PC2_PCR and PORT5_IOCR0_PC2_OE */
WR_REG(PORT5->IOCR4, PORT_IOCR_PC3_OE_Msk, PORT_IOCR_PC3_OE_Pos, PORT_IOCR_OE1); /* P5.7 : PORT5_IOCR4_PC7_OE */
}
/* This Function initializes the CCU4_CCy slice and the App. Local function
* is used to initialize all the instances of the app.
*/
status_t CNT001_lInit(const CNT001_HandleType *HandlePtr )
{
status_t status = (uint32_t)CNT001_OPER_NOT_ALLOWED_ERROR;
CCU4_CC4_TypeDef *CCU4Ptr; /*Pointer to the CCU4 Structure */
CCU4_GLOBAL_TypeDef *CCU4KernelPtr; /* Pointer to the CCU4 Kernel Structure */
CCU4Ptr = HandlePtr->CC4Ptr;
CCU4KernelPtr = HandlePtr->CC4KernalPtr;
DBG002_FUNCTION_ENTRY(APP_GID, (uint32_t)CNT001_FUNCTION_ENTRY);
do
{
/*<<<DD_CNT001_API_1_1>>>*/
if (HandlePtr->DynamicHandlePtr->State != CNT001_UNINITIALIZED)
{
DBG002_INFO(APP_GID, DBG002_MESSAGEID_LITERAL, CNT001_STATUS_LEN, &status);
break;
}/* End of "if(HandlePtr->DynamicHandlePtr->State != CNT001_UNINITIALIZED)"*/
/*<<<DD_CNT001_API_1_2>>>*/
/* Set the Input Selector Register */
/* Step1: Clear the EV0EM & LPF0M bit fields */
CCU4Ptr->INS &= (uint32_t)~((CCU4_CC4_INS_EV0EM_Msk )| \
(uint32_t)(CCU4_CC4_INS_LPF0M_Msk ) \
);
/*Step2: Set the Bit */
CCU4Ptr->INS |= (uint32_t)((((uint32_t)HandlePtr->CountingEventEdge <<
CCU4_CC4_INS_EV0EM_Pos)& (uint32_t)CCU4_CC4_INS_EV0EM_Msk) | \
(((uint32_t)HandlePtr->Lpf << \
CCU4_CC4_INS_LPF0M_Pos)& (uint32_t)CCU4_CC4_INS_LPF0M_Msk)
);
/* Set CNT001_EVENT0 as External Counting function in CMC Register*/
WR_REG(CCU4Ptr->CMC, (uint32_t)CCU4_CC4_CMC_CNTS_Msk,\
(uint32_t)CCU4_CC4_CMC_CNTS_Pos,(uint32_t)CNT001_EVENT0);
/* If Gating enabled , Set CNT001_EVENT1 as external gating signal*/
if (HandlePtr->ExternalGatingSignal)
{
CCU4Ptr->INS |= (((uint32_t)HandlePtr->GatingLevel << CCU4_CC4_INS_EV1LM_Pos )\
& (uint32_t)CCU4_CC4_INS_EV1LM_Msk);
CCU4Ptr->CMC |= (((uint32_t)CNT001_EVENT1 << CCU4_CC4_CMC_GATES_Pos)\
& (uint32_t)CCU4_CC4_CMC_GATES_Msk);
if((uint32_t)HandlePtr->GatingLevel == (uint8_t)RESET)
{
CCU4Ptr->INS |= (((uint32_t)0x01 << CCU4_CC4_INS_EV1EM_Pos )\
& (uint32_t)CCU4_CC4_INS_EV1EM_Msk);
}
else
{
CCU4Ptr->INS |= (((uint32_t)0x02 << CCU4_CC4_INS_EV1EM_Pos )\
& (uint32_t)CCU4_CC4_INS_EV1EM_Msk);
}
}/*End of "if( HandlePtr->ExternalGatingSignal)" */
/* Clear the Timer Values( DITC, TCC, TRBC bit fields in TCCLR Register ) */
CCU4Ptr->TCCLR |= CNT001_CCU4_TCCLR_CLEAR;
/* Set edge-aligned mode in the TC Register */
WR_REG(CCU4Ptr->TC,(uint32_t)CCU4_CC4_TC_TCM_Msk,\
(uint32_t)CCU4_CC4_TC_TCM_Pos,(uint32_t)CNT001_EDGE_ALIGNED_MODE );
/*Set Compare register value with the user defined value */
WR_REG(CCU4Ptr->CRS, (uint32_t)CCU4_CC4_CRS_CRS_Msk,\
(uint32_t)CCU4_CC4_CRS_CRS_Pos, (uint32_t)HandlePtr->CountMatch);
/* Set Period register Value as maximum*/
WR_REG(CCU4Ptr->PRS, (uint32_t)CCU4_CC4_PRS_PRS_Msk,\
(uint32_t)CCU4_CC4_PRS_PRS_Pos, (uint32_t)CNT001_MAX_EVENTS);
/* Request SW shadow transfer */
CCU4KernelPtr->GCSS |=
(uint32_t)(((uint32_t)0x01 << ((uint32_t)4 * (uint32_t)HandlePtr->CCUInUse)) |
((uint32_t)0x01 << (((uint32_t)4 * (uint32_t)HandlePtr->CCUInUse) + 1U)) |
((uint32_t)0x01 << (((uint32_t)4 * (uint32_t)HandlePtr->CCUInUse) + 2U)));
/* Clear all interrupts */
CCU4Ptr->SWR = CNT001_ALL_CCU4_INTR_CLEAR;
/* Enable configured interrupts */
CCU4Ptr->INTE |= HandlePtr->InterruptControl;
/*Initialize global variables */
HandlePtr->DynamicHandlePtr->EvtCounterValue = 0x00U;
HandlePtr->DynamicHandlePtr->NewCountMatch = HandlePtr->CountMatch;
/* Set the App State to Initialized */
HandlePtr->DynamicHandlePtr->State = CNT001_INITIALIZED;
status = (uint32_t)DAVEApp_SUCCESS;
}while(0);
DBG002_FUNCTION_EXIT(APP_GID, (uint32_t)CNT001_FUNCTION_EXIT);
return status;
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[0] |= (uint32_t) RD_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,6);
WR_REG(USIC0_CH0->DX3CR, USIC_CH_DX3CR_DSEL_Msk, USIC_CH_DX3CR_DSEL_Pos,5);
WR_REG(USIC0_CH0->DX5CR, USIC_CH_DX5CR_DSEL_Msk, USIC_CH_DX5CR_DSEL_Pos,4);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x05000020); /* DPTR = 32, SIZE = 5 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x05000000); /* DPTR = 0, SIZE = 5 */
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[0]);
//********* Capture/Compare Unit 4 (CAPCOM4) CONFIGURATIONS *************************
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P1.0 : PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P1.1 : PORT1_IOCR0_PC1_OE */
WR_REG(PORT1->IOCR4, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P1.5 : PORT1_IOCR4_PC5_PCR and PORT1_IOCR4_PC5_OE */
//********* Capture/Compare Unit 8 (CAPCOM8) CONFIGURATIONS *************************
/*VADC GROUP0 Mux Related SFR/Bitfields Configurations*/
/*VADC GROUP1 Mux Related SFR/Bitfields Configurations*/
/*VADC GROUP2 Mux Related SFR/Bitfields Configurations*/
/*VADC GROUP3 Mux Related SFR/Bitfields Configurations*/
/*VADC GLOBAL RESULT Mux Related SFR/Bitfields Configurations*/
/*VADC BACKGROUND Source Mux Related SFR/Bitfields Configurations*/
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[0] |= (uint32_t) RD_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[1] |= (uint32_t) RD_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,4);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x01000006); /* DPTR = 6, SIZE = 1 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x01000004); /* DPTR = 4, SIZE = 1 */
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH1->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,5);
WR_REG(USIC0_CH1->DX1CR, USIC_CH_DX1CR_DSEL_Msk, USIC_CH_DX1CR_DSEL_Pos,4);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 2 is selected for Protocol specific event
WR_REG(USIC0_CH1->INPR, USIC_CH_INPR_PINP_Msk, USIC_CH_INPR_PINP_Pos,2);
//Interrupt node 1 is selected for Standard receive buffer event
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_SRBINP_Msk, USIC_CH_RBCTR_SRBINP_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x01000002); /* DPTR = 2, SIZE = 1 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x01000000); /* DPTR = 0, SIZE = 1 */
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[0]);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[1]);
//********* Capture/Compare Unit 4 (CAPCOM4) CONFIGURATIONS *************************
// Configuring CCU40 CC41INS - Input Selector Configuration
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyB);
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyB);
// Configuring CCU40 CC42INS - Input Selector Configuration
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyB);
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyB);
// Configuring CCU40 CC43INS - Input Selector Configuration
WR_REG(CCU40_CC43->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyB);
WR_REG(CCU40_CC43->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyB);
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT0->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P0.0 : PORT0_IOCR0_PC0_OE */
WR_REG(PORT0->IOCR4, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x11U); /*P0.4 : PORT0_IOCR4_PC4_PCR and PORT0_IOCR4_PC4_OE */
WR_REG(PORT0->IOCR4, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x16U); /*P0.5 : PORT0_IOCR4_PC5_PCR and PORT0_IOCR4_PC5_OE */
WR_REG(PORT0->IOCR4, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x11U); /*P0.6 : PORT0_IOCR4_PC6_PCR and PORT0_IOCR4_PC6_OE */
WR_REG(PORT0->IOCR8, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x14U); /*P0.10 : PORT0_IOCR8_PC10_PCR and PORT0_IOCR8_PC10_OE */
WR_REG(PORT0->IOCR12, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x11U); /*P0.12 : PORT0_IOCR12_PC12_PCR and PORT0_IOCR12_PC12_OE */
WR_REG(PORT0->IOCR12, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P0.13 : PORT0_IOCR12_PC13_OE */
WR_REG(PORT1->IOCR0, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x16U); /*P1.0 : PORT1_IOCR0_PC0_PCR and PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P1.1 : PORT1_IOCR0_PC1_PCR and PORT1_IOCR0_PC1_OE */
WR_REG(PORT1->IOCR0, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x12U); /*P1.2 : PORT1_IOCR0_PC2_PCR and PORT1_IOCR0_PC2_OE */
WR_REG(PORT1->IOCR0, 0xb8000000U, PORT_IOCR_PC3_PCR_Pos, 0x12U); /*P1.3 : PORT1_IOCR0_PC3_PCR and PORT1_IOCR0_PC3_OE */
WR_REG(PORT2->PDISC, PORT2_PDISC_PDIS10_Msk, PORT2_PDISC_PDIS10_Pos, PORT_PDISC_PDIS0); /* P2.10 : PORT2_PDISC_PDIS10 */
WR_REG(PORT2->IOCR8, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x17U); /*P2.10 : PORT2_IOCR8_PC10_PCR and PORT2_IOCR8_PC10_OE */
WR_REG(PORT2->PDISC, PORT2_PDISC_PDIS11_Msk, PORT2_PDISC_PDIS11_Pos, PORT_PDISC_PDIS0); /* P2.11 : PORT2_PDISC_PDIS11 */
WR_REG(PORT2->IOCR8, 0xb8000000U, PORT_IOCR_PC3_PCR_Pos, 0x16U); /*P2.11 : PORT2_IOCR8_PC11_PCR and PORT2_IOCR8_PC11_OE */
/* BCCU Macro definitions: */
WR_REG(BCCU0_CH0->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 7); /* BCCU_CHCONFIG0_DSEL */
WR_REG(BCCU0_CH2->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 7); /* BCCU_CHCONFIG2_DSEL */
WR_REG(BCCU0_CH3->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 2); /* BCCU_CHCONFIG3_DSEL */
WR_REG(BCCU0_CH4->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 2); /* BCCU_CHCONFIG4_DSEL */
WR_REG(BCCU0_CH5->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 2); /* BCCU_CHCONFIG5_DSEL */
WR_REG(BCCU0_CH6->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 7); /* BCCU_CHCONFIG6_DSEL */
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
/*
* CAN peripheral configuration:
*/
//Node2 configuration:
WR_REG(CAN_NODE2->NIPR, CAN_NODE_NIPR_ALINP_Msk, CAN_NODE_NIPR_ALINP_Pos, SRN1);
//Message object 35 configuration:
WR_REG(CAN_MO35->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
//Message object 36 configuration:
WR_REG(CAN_MO36->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
//Message object 37 configuration:
WR_REG(CAN_MO37->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
//Message object 38 configuration:
WR_REG(CAN_MO38->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
/* Macros which makes the CAN peripheral to exit from the INITIALISATION mode to NORMAL mode */
#ifdef CAN_NODE0_ENABLE
CAN_Handle0_NODE();
#endif
#ifdef CAN_NODE1_ENABLE
CAN_Handle1_NODE();
#endif
#ifdef CAN_NODE2_ENABLE
CAN_Handle2_NODE();
#endif
/*
* POSIF0 peripheral configuration:
*/
//POSIF0 configuration:
WR_REG(POSIF0->PCONF, POSIF_PCONF_INSEL0_Msk, POSIF_PCONF_INSEL0_Pos, INSIGNAL1);
WR_REG(POSIF0->PCONF, POSIF_PCONF_INSEL1_Msk, POSIF_PCONF_INSEL1_Pos, INSIGNAL1);
/*
* POSIF1 peripheral configuration:
*/
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[0] |= (uint32_t) RD_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[2] |= (uint32_t) RD_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[3] |= (uint32_t) RD_REG(USIC1_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC1_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,3);
//Standard transmit buffer event is enabled.
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_STBIEN_Msk, USIC_CH_TBCTR_STBIEN_Pos,1);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 3 is selected for Standard transmit buffer event
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_STBINP_Msk, USIC_CH_TBCTR_STBINP_Pos,3);
//Interrupt node 5 is selected for Standard receive buffer event
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBINP_Msk, USIC_CH_RBCTR_SRBINP_Pos,5);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x04000010); /* DPTR = 16, SIZE = 4 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x04000000); /* DPTR = 0, SIZE = 4 */
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC1_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,2);
//Standard transmit buffer event is enabled.
WR_REG(USIC1_CH0->TBCTR, USIC_CH_TBCTR_STBIEN_Msk, USIC_CH_TBCTR_STBIEN_Pos,1);
//Standard receive buffer event is enabled.
WR_REG(USIC1_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 1 is selected for Standard transmit buffer event
WR_REG(USIC1_CH0->TBCTR, USIC_CH_TBCTR_STBINP_Msk, USIC_CH_TBCTR_STBINP_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC1_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x04000010); /* DPTR = 16, SIZE = 4 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC1_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x04000000); /* DPTR = 0, SIZE = 4 */
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC1_CH1->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,3);
//Standard transmit buffer event is enabled.
WR_REG(USIC1_CH1->TBCTR, USIC_CH_TBCTR_STBIEN_Msk, USIC_CH_TBCTR_STBIEN_Pos,1);
//Standard receive buffer event is enabled.
WR_REG(USIC1_CH1->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 3 is selected for Standard transmit buffer event
WR_REG(USIC1_CH1->TBCTR, USIC_CH_TBCTR_STBINP_Msk, USIC_CH_TBCTR_STBINP_Pos,3);
//Interrupt node 2 is selected for Standard receive buffer event
WR_REG(USIC1_CH1->RBCTR, USIC_CH_RBCTR_SRBINP_Msk, USIC_CH_RBCTR_SRBINP_Pos,2);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC1_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x04000030); /* DPTR = 48, SIZE = 4 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC1_CH1->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x04000020); /* DPTR = 32, SIZE = 4 */
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[0]);
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[2]);
WR_REG(USIC1_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[3]);
//********* Capture/Compare Unit 4 (CAPCOM4) CONFIGURATIONS *************************
// Configuring CCU40 CC41INS - Input Selector Configuration
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyE);
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyF);
// Configuring CCU40 CC42INS - Input Selector Configuration
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyF);
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyM);
// Configuring CCU40_CC40SRS = Service Request Selector
WR_REG(CCU40_CC40->SRS, CCU4_CC4_SRS_POSR_Msk, CCU4_CC4_SRS_POSR_Pos, CCU_SR1);
// Configuring CCU40_CC41SRS = Service Request Selector
WR_REG(CCU40_CC41->SRS, CCU4_CC4_SRS_CMSR_Msk, CCU4_CC4_SRS_CMSR_Pos, CCU_SR2);
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT0->IOCR0, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P0.1 : PORT0_IOCR0_PC1_PCR and PORT0_IOCR0_PC1_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P1.0 : PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P1.1 : PORT1_IOCR0_PC1_OE */
WR_REG(PORT2->IOCR12, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x12U); /*P2.14 : PORT2_IOCR12_PC14_PCR and PORT2_IOCR12_PC14_OE */
WR_REG(PORT5->IOCR0, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x11U); /*P5.1 : PORT5_IOCR0_PC1_PCR and PORT5_IOCR0_PC1_OE */
}
/* Function to configure message object registers */
static void CAN001_lConfigMORegs(const CAN001_MessageHandleType* MsgObjptr, uint8_t MsgObjnr)
{
CAN_MO_TypeDef* CAN_MOxRegs = GET_MO_OFFSET(MsgObjnr);
uint32_t Count = 0U;
/* <<<DD_CAN001_nonAPI_3>>> */
/* Disable Message object */
CAN_MOxRegs->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk;
if ((CAN_FrameType)MsgObjptr->IDExten == STANDARDTYPE)
{
/* Configure standard identifier and identifier mask*/
CAN_MOxRegs->MOAR = ((((uint32_t)2UL << CAN_MO_MOAR_PRI_Pos) & \
(uint32_t)CAN_MO_MOAR_PRI_Msk) | \
((uint32_t)(MsgObjptr->Identifier << CAN_MO_MOAR_STDID_Pos) \
& (uint32_t)CAN_MO_MOAR_STDID_Msk));
if(MsgObjptr->IDEMask == 1U)
{
CAN_MOxRegs->MOAMR = ((((uint32_t)1UL << CAN_MO_MOAMR_MIDE_Pos) & \
(uint32_t)CAN_MO_MOAMR_MIDE_Msk) | \
((uint32_t)(MsgObjptr->IDMask << CAN_MO_MOAR_STDID_Pos) \
& (uint32_t)CAN_MO_MOAR_STDID_Msk));
}
else
{
CAN_MOxRegs->MOAMR = ((((uint32_t)0UL << CAN_MO_MOAMR_MIDE_Pos) & \
(uint32_t)CAN_MO_MOAMR_MIDE_Msk) | \
((uint32_t)CAN_MO_MOAMR_AM_Msk & (uint32_t)MsgObjptr->IDMask));
}
} /* if (MsgObjptr->IDExten == STANDARDTYPE) */
else
{
/* Configure Extended identifier and identifier mask*/
CAN_MOxRegs->MOAR = ((((uint32_t)2UL << CAN_MO_MOAR_PRI_Pos) & \
(uint32_t)CAN_MO_MOAR_PRI_Msk) | \
((uint32_t)(CAN_MO_MOAR_ID_Msk & MsgObjptr->Identifier)) | \
(((uint32_t)1UL << CAN_MO_MOAR_IDE_Pos ) & \
(uint32_t)CAN_MO_MOAR_IDE_Msk));
CAN_MOxRegs->MOAMR = (((uint32_t)((uint32_t)MsgObjptr->IDEMask << CAN_MO_MOAMR_MIDE_Pos) & \
(uint32_t)CAN_MO_MOAMR_MIDE_Msk) | \
(uint32_t)(CAN_MO_MOAMR_AM_Msk & MsgObjptr->IDMask));
}
/* Check whether message object is transmit message object */
/*<<<DD_CAN001_API_3_2>>>*/
if (MsgObjptr->MsgObjType == TRANSMSGOBJ)
{
/* Configure data length */
WR_REG(CAN_MOxRegs->MOFCR, (uint32_t)CAN_MO_MOFCR_DLC_Msk, \
CAN_MO_MOFCR_DLC_Pos, (uint32_t)MsgObjptr->DataLength);
/* Configure Data registers*/
for(Count = 0U; Count < MsgObjptr->DataLength; Count++)
{
if(Count < 4U)
{
WR_REG(CAN_MOxRegs->MODATAL, (uint32_t)((uint32_t)CAN_MO_MODATAL_DB0_Msk << (Count*8U)), \
(Count*8U),(uint32_t)MsgObjptr->data[Count]);
}
else
{
WR_REG(CAN_MOxRegs->MODATAH, (uint32_t)(CAN_MO_MODATAL_DB0_Msk << ((Count-4U)*8U)), \
((Count-4U)*8U), (uint32_t)MsgObjptr->data[Count]);
} /* if(Count < 4) */
} /* for(Count = 0; Count < MsgObjptr->DataLength; Count++) */
/* Set MO as Transmit message object and set NEWDAT bit */
CAN_MOxRegs->MOCTR = (CAN_MO_MOCTR_SETDIR_Msk | \
CAN_MO_MOCTR_SETNEWDAT_Msk);
}/*if (MsgType == TRANSMSGOBJ)*/
/*<<<DD_CAN001_API_3_3>>>*/
else
{
/* Set MO as Receive message object and set RXEN bit */
CAN_MOxRegs->MOCTR = CAN_MO_MOCTR_RESDIR_Msk;
} /*if(MsgType == RECMSGOBJ)*/
/* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */
CAN_MOxRegs->MOCTR = (CAN_MO_MOCTR_SETTXEN0_Msk | \
CAN_MO_MOCTR_SETTXEN1_Msk | \
CAN_MO_MOCTR_SETRXEN_Msk | \
CAN_MO_MOCTR_SETMSGVAL_Msk );
}
/**
* This function initializes an instance of the app
*/
status_t PWMSP003_lInit(const PWMSP003_HandleType* HandlePtr)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
uint32_t Temp;
PWMSP003_EdgeTriggerType EdgeSelection = PWMSP003_NO_TRIGGER;
PWMSP003_ActiveLevelType LevelSelection = PWMSP003_ACTIVE_ON_HIGH;
do
{
if (HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
break;
}
HandlePtr->CC4yRegsPtr->TCCLR = PWMSP003_SLICE_CLEAR;
if(HandlePtr->kEvent0Function != PWMSP003_NO_FUNCTION)
{
if(HandlePtr->kEvent0Function == PWMSP003_EXTERNAL_START)
{
EdgeSelection = HandlePtr->kStartEdge;
}
else if(HandlePtr->kEvent0Function == PWMSP003_EXTERNAL_STOP)
{
EdgeSelection = HandlePtr->kStopEdge;
}
else if(HandlePtr->kEvent0Function == PWMSP003_EXTERNAL_LOAD)
{
EdgeSelection = HandlePtr->kLoadEventEdge;
}
else if(HandlePtr->kEvent0Function == PWMSP003_EXTERNAL_COUNT)
{
EdgeSelection = HandlePtr->kCountEventEdge;
}
else
{
EdgeSelection = PWMSP003_RISING_EDGE;
}
if(HandlePtr->kEvent0Function == PWMSP003_EXTERNAL_COUNT_DIRECTION)
{
LevelSelection = HandlePtr->kCntDirActiveLevel;
}
else if(HandlePtr->kEvent0Function == PWMSP003_EXTERNAL_MODULATION)
{
LevelSelection = HandlePtr->kModulationActiveLevel;
}
else if(HandlePtr->kEvent0Function == PWMSP003_EXTERNAL_GATING)
{
LevelSelection = HandlePtr->kGateEventActiveLevel;
}
else
{
/** */
}
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_EV0EM_Msk,\
(uint32_t)CCU4_CC4_INS_EV0EM_Pos, (uint32_t)EdgeSelection);
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_EV0LM_Msk,\
(uint32_t)CCU4_CC4_INS_EV0LM_Pos, (uint32_t)LevelSelection);
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_LPF0M_Msk,\
(uint32_t)CCU4_CC4_INS_LPF0M_Pos, HandlePtr->kEvent0_lpfconfig);
if(HandlePtr->kEvent0Function != PWMSP003_EXTERNAL_START)
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC,\
(uint32_t)(CCU4_CC4_CMC_STRTS_Msk << HandlePtr->kEvent0Function),\
(uint32_t)(CCU4_CC4_CMC_STRTS_Pos + HandlePtr->kEvent0Function),\
PWMSP003_EVENT_0);
}
}
/* Reset to default */
EdgeSelection = PWMSP003_NO_TRIGGER;
LevelSelection = PWMSP003_ACTIVE_ON_HIGH;
if(HandlePtr->kEvent1Function != PWMSP003_NO_FUNCTION)
{
if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_START)
{
EdgeSelection = HandlePtr->kStartEdge;
}
else if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_STOP)
{
EdgeSelection = HandlePtr->kStopEdge;
}
else if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_LOAD)
{
EdgeSelection = HandlePtr->kLoadEventEdge;
}
else if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_COUNT)
{
EdgeSelection = HandlePtr->kCountEventEdge;
}
else
{
EdgeSelection = PWMSP003_RISING_EDGE;
}
if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_COUNT_DIRECTION)
{
LevelSelection = HandlePtr->kCntDirActiveLevel;
}
else if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_MODULATION)
{
LevelSelection = HandlePtr->kModulationActiveLevel;
}
else if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_OVERRIDE)
{
LevelSelection = HandlePtr->kOverrideActiveLevel;
}
else if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_GATING)
{
LevelSelection = HandlePtr->kGateEventActiveLevel;
}
else
{
/** */
}
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_EV1EM_Msk,\
(uint32_t)CCU4_CC4_INS_EV1EM_Pos, (uint32_t)EdgeSelection);
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_EV1LM_Msk,\
(uint32_t)CCU4_CC4_INS_EV1LM_Pos, (uint32_t)LevelSelection);
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_LPF1M_Msk,\
(uint32_t)CCU4_CC4_INS_LPF1M_Pos, HandlePtr->kEvent1_lpfconfig);
if(HandlePtr->kEvent1Function != PWMSP003_EXTERNAL_START)
{
/* Override Config in CMC Register is only one bit each */
/* START/STOP etc. are 2 bits each */
if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_OVERRIDE)
{
/* Mask for Trap, 1 bit */
Temp = PWMSP003_OVERRIDEEVENT_BITMASK;
}
else
{
/* Mask for START,STOP etc. functions, 2 bits */
Temp = PWMSP003_STARTEVENT_BITMASK;
}
if(HandlePtr->kEvent1Function == PWMSP003_EXTERNAL_OVERRIDE)
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC,\
(uint32_t)((CCU4_CC4_CMC_STRTS_Msk & Temp) <<\
HandlePtr->kEvent1Function),\
(uint32_t)(CCU4_CC4_CMC_STRTS_Pos + HandlePtr->kEvent1Function),\
0x01U);
}
else
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC,\
(uint32_t)((CCU4_CC4_CMC_STRTS_Msk & Temp) <<\
HandlePtr->kEvent1Function),\
(uint32_t)(CCU4_CC4_CMC_STRTS_Pos + HandlePtr->kEvent1Function),\
PWMSP003_EVENT_1);
}
}
}
/* Reset to default */
EdgeSelection = PWMSP003_NO_TRIGGER;
LevelSelection = PWMSP003_ACTIVE_ON_HIGH;
if(HandlePtr->kEvent2Function != PWMSP003_NO_FUNCTION)
{
if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_START)
{
EdgeSelection = HandlePtr->kStartEdge;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_STOP)
{
EdgeSelection = HandlePtr->kStopEdge;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_LOAD)
{
EdgeSelection = HandlePtr->kLoadEventEdge;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_COUNT)
{
EdgeSelection = HandlePtr->kCountEventEdge;
}
else
{
EdgeSelection = PWMSP003_RISING_EDGE;
}
if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_COUNT_DIRECTION)
{
LevelSelection = HandlePtr->kCntDirActiveLevel;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_TRAP)
{
LevelSelection = HandlePtr->kTrapLevel;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_MODULATION)
{
LevelSelection = HandlePtr->kModulationActiveLevel;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_OVERRIDE)
{
LevelSelection = HandlePtr->kOverrideActiveLevel;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_GATING)
{
LevelSelection = HandlePtr->kGateEventActiveLevel;
}
else
{
/** */
}
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_EV2EM_Msk,\
(uint32_t)CCU4_CC4_INS_EV2EM_Pos, (uint32_t)EdgeSelection);
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_EV2LM_Msk,\
(uint32_t)CCU4_CC4_INS_EV2LM_Pos, (uint32_t)LevelSelection);
WR_REG(HandlePtr->CC4yRegsPtr->INS, (uint32_t)CCU4_CC4_INS_LPF2M_Msk,\
(uint32_t)CCU4_CC4_INS_LPF2M_Pos, HandlePtr->kEvent2_lpfconfig);
if(HandlePtr->kEvent2Function != PWMSP003_EXTERNAL_START)
{
/* Trap and Override Config in CMC Register is only one bit each */
/* START/STOP etc. are 2 bits each */
if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_OVERRIDE)
{
/* Mask for Trap, 1 bit */
Temp = PWMSP003_OVERRIDEEVENT_BITMASK;
}
else if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_TRAP)
{
/* Mask for Trap, 1 bit */
Temp = PWMSP003_TRAPEVENT_BITMASK;
}
else
{
/* Mask for START,STOP etc. functions, 2 bits */
Temp = PWMSP003_STARTEVENT_BITMASK;
}
if(HandlePtr->kEvent2Function == PWMSP003_EXTERNAL_OVERRIDE)
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC,\
(uint32_t)((CCU4_CC4_CMC_STRTS_Msk & Temp) <<\
HandlePtr->kEvent2Function),\
(uint32_t)(CCU4_CC4_CMC_STRTS_Pos + HandlePtr->kEvent2Function),\
0x01U);
}
else
{
WR_REG(HandlePtr->CC4yRegsPtr->CMC,\
(uint32_t)((CCU4_CC4_CMC_STRTS_Msk & Temp) <<\
HandlePtr->kEvent2Function),\
(uint32_t)(CCU4_CC4_CMC_STRTS_Pos + HandlePtr->kEvent2Function),\
PWMSP003_EVENT_2);
}
}
}
/* Slice Timer Control */
HandlePtr->CC4yRegsPtr->TC &= ~(CCU4_CC4_TC_TCM_Msk |\
CCU4_CC4_TC_TSSM_Msk | CCU4_CC4_TC_CMOD_Msk |\
CCU4_CC4_TC_STRM_Msk | CCU4_CC4_TC_ENDM_Msk | CCU4_CC4_TC_DITHE_Msk);
/* Timer control configurations */
HandlePtr->CC4yRegsPtr->TC |= (((uint32_t)HandlePtr->CountingModeType <<\
CCU4_CC4_TC_TCM_Pos) & CCU4_CC4_TC_TCM_Msk) |\
(((uint32_t)HandlePtr->kTimerMode << CCU4_CC4_TC_TSSM_Pos) &\
CCU4_CC4_TC_TSSM_Msk)|(((uint32_t)PWMSP003_COMPARE_MODE <<\
CCU4_CC4_TC_CMOD_Pos)& CCU4_CC4_TC_CMOD_Msk) |\
(((uint32_t)HandlePtr->ExtStartConfigType <<CCU4_CC4_TC_STRM_Pos) &\
CCU4_CC4_TC_STRM_Msk)|(((uint32_t)HandlePtr->ExtStopConfigType <<\
CCU4_CC4_TC_ENDM_Pos)& CCU4_CC4_TC_ENDM_Msk);
/*Set the dither mode setting*/
WR_REG(HandlePtr->CC4yRegsPtr->TC,(uint32_t)CCU4_CC4_TC_DITHE_Msk,\
(uint32_t)CCU4_CC4_TC_DITHE_Pos, HandlePtr->kDitherSetting);
/* Set the floating point prescaler mode */
WR_REG(HandlePtr->CC4yRegsPtr->TC,(uint32_t)CCU4_CC4_TC_FPE_Msk,\
(uint32_t)CCU4_CC4_TC_FPE_Pos, HandlePtr->kPrescalerMode);
WR_REG(HandlePtr->CC4yRegsPtr->DITS,(uint32_t)CCU4_CC4_DITS_DCVS_Msk,\
(uint32_t)CCU4_CC4_DITS_DCVS_Pos, HandlePtr->kDitherCompare);
/* Configure Trap mode */
WR_REG(HandlePtr->CC4yRegsPtr->TC, (uint32_t)CCU4_CC4_TC_TRPSE_Msk,\
(uint32_t)CCU4_CC4_TC_TRPSE_Pos, HandlePtr->kTrapSync);
/* Configure Trap exit mode */
WR_REG(HandlePtr->CC4yRegsPtr->TC, (uint32_t)CCU4_CC4_TC_TRPSW_Msk,\
(uint32_t)CCU4_CC4_TC_TRPSW_Pos, HandlePtr->kTrapExitControl);
/* External modulation sync */
WR_REG(HandlePtr->CC4yRegsPtr->TC, (uint32_t)CCU4_CC4_TC_EMS_Msk,\
(uint32_t)CCU4_CC4_TC_EMS_Pos, HandlePtr->kModulationSync);
/* External modulation type */
WR_REG(HandlePtr->CC4yRegsPtr->TC, (uint32_t)CCU4_CC4_TC_EMT_Msk,\
(uint32_t)CCU4_CC4_TC_EMT_Pos, HandlePtr->kModulationMode);
/* Set the prescaler divider and passive level of the o/p signal */
WR_REG(HandlePtr->CC4yRegsPtr->PSC, (uint32_t)CCU4_CC4_PSC_PSIV_Msk,\
(uint32_t)CCU4_CC4_PSC_PSIV_Pos, HandlePtr->kCCUPrescaler);
/* if Selected prescaler is Floating Prescaler, set FP register */
if(HandlePtr->kPrescalerMode ==
(PWMSP003_PrescalerModeType)PWMSP003_FLOATING_PRESCALER)
{
HandlePtr->CC4yRegsPtr->FPCS =\
(uint32_t)HandlePtr->kFloatingPrescalepcmpvalue;
}
HandlePtr->CC4yRegsPtr->PSL = HandlePtr->kPassiveLevel;
/* Setting period register's value */
HandlePtr->CC4yRegsPtr->PRS = (uint32_t)(HandlePtr->kPeriodVal & 0xFFFFU);
/*Setting compare register's value*/
HandlePtr->CC4yRegsPtr->CRS = (uint32_t)(HandlePtr->kCompareValue &0xFFFFU);
HandlePtr->CC4yRegsPtr->SWR |= PWMSP003_ALL_CCU4_INTR_CLEAR;
/* Applying Interrupt settings */
HandlePtr->CC4yRegsPtr->INTE |= HandlePtr->InterruptControl;
/* Request SW shadow transfer for period, compare, dither and prescaler */
HandlePtr->CC4yKernRegsPtr->GCSS |=\
(((uint32_t)0x1U << (PWMSP003_NO_OF_SLICES * (uint32_t)HandlePtr->Slice)) |\
((uint32_t)0x1U <<\
((PWMSP003_NO_OF_SLICES * (uint32_t)HandlePtr->Slice) + (uint32_t)0x1U)) |\
((uint32_t)0x1U <<\
((PWMSP003_NO_OF_SLICES * (uint32_t)HandlePtr->Slice) + (uint32_t)0x2U)));
/* Multi channel shadow transfer enable or disable */
WR_REG(HandlePtr->CC4yRegsPtr->TC, (uint32_t)CCU4_CC4_TC_MCME_Msk,\
(uint32_t)CCU4_CC4_TC_MCME_Pos, HandlePtr->kMCMode);
/* Multi channel shadow transfer source select */
WR_REG(HandlePtr->CC4yKernRegsPtr->GCTRL,
(uint32_t)(CCU4_GCTRL_MSE0_Msk << HandlePtr->Slice),\
(uint32_t)(CCU4_GCTRL_MSE0_Pos + HandlePtr->Slice),\
(uint32_t)HandlePtr->kMCModeShadowRequest);
/* Multi channel shadow transfer configuration */
WR_REG(HandlePtr->CC4yKernRegsPtr->GCTRL,
(uint32_t)CCU4_GCTRL_MSDE_Msk,\
(uint32_t)CCU4_GCTRL_MSDE_Pos,
(uint32_t)HandlePtr->kMCModeShadowConfig);
Status = (uint32_t)DAVEApp_SUCCESS;
HandlePtr->DynamicDataType->StateType = PWMSP003_INITIALIZED;
} while (0);
return Status;
}
