/**
* getEfuseByte - Get Efuse Byte
*
*
* @param[in] Index - Efuse Index value
*
*/
UINT8
getEfuseByte (
IN UINT8 Index
)
{
UINT8 Data;
WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, &Index);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, &Data);
return Data;
}
/**
* getEfuseStatue - Get Efuse status
*
*
* @param[in] Value - Return Chip strap status
*
*/
VOID
getEfuseStatus (
IN VOID* Value
)
{
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
}
signed BootParameters1 (struct plc * plc)
{
struct pib_header pib_header;
uint32_t offset;
if (lseek (plc->PIB.file, 0, SEEK_SET))
{
error ((plc->flags & PLC_BAILOUT), errno, FILE_CANTHOME, plc->PIB.name);
}
if (read (plc->PIB.file, &pib_header, sizeof (pib_header)) != sizeof (pib_header))
{
error ((plc->flags & PLC_BAILOUT), errno, FILE_CANTREAD, plc->PIB.name);
}
if (lseek (plc->PIB.file, 0, SEEK_SET))
{
error ((plc->flags & PLC_BAILOUT), errno, FILE_CANTHOME, plc->PIB.name);
}
#if 1
/*
* this code is a fix to accommodate PIB relocation in memory; it is not needed when
* the PIB is stored in an NVM file since the memory address is recorded in the image
* header;
*/
if (BE16TOH (*(uint16_t *)(&pib_header)) < 0x0305)
{
offset = LEGACY_PIBOFFSET;
}
else if (BE16TOH (*(uint16_t *)(&pib_header)) < 0x0500)
{
offset = INT6x00_PIBOFFSET;
}
else
{
offset = AR7x00_PIBOFFSET;
}
#endif
if (plc->hardwareID < CHIPSET_AR7400)
{
if (WriteMEM (plc, &plc->PIB, 0, offset, LE16TOH (pib_header.PIBLENGTH)))
{
return (-1);
}
return (0);
}
if (WriteExecutePIB (plc, offset, &pib_header))
{
return (-1);
}
return (0);
}
VOID
RWMEM (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
ReadMEM (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WriteMEM (Address, OpFlag, &Result);
}
VOID
SetAcpiPma (
IN UINT8 pmaControl
)
{
UINT16 pmaBase;
UINT16 dwValue;
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
dwValue &= ~BIT6;
WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, &pmaBase);
WriteIo8 (pmaBase, pmaControl);
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, ~BIT7, pmaControl << 7);
}
signed EmulateHost (struct plc * plc)
{
struct channel * channel = (struct channel *)(plc->channel);
struct message * message = (struct message *)(plc->message);
static char const * actions [] =
{
"start device",
"store firmware",
"store parameters",
"update host",
"config memory",
"restore defaults",
"unknown"
};
#ifndef __GNUC__
#pragma pack (push,1)
#endif
struct __packed vs_host_action_ind
{
struct ethernet_hdr ethernet;
struct qualcomm_hdr qualcomm;
uint8_t MACTION;
uint8_t MAJOR_VERSION;
uint8_t MINOR_VERSION;
}
* indicate = (struct vs_host_action_ind *) (message);
#if 0
struct __packed vs_host_action_rsp
{
struct ethernet_hdr ethernet;
struct qualcomm_hdr qualcomm;
uint8_t MSTATUS;
}
* response = (struct vs_host_action_rsp *) (message);
#endif
#ifndef __GNUC__
#pragma pack (pop)
#endif
struct nvm_header1 nvm_header;
struct pib_header pib_header;
uint32_t offset;
char const * PIB = plc->PIB.name;
char const * NVM = plc->NVM.name;
signed timer = channel->timeout;
signed status = 0;
Request (plc, "Waiting for Host Action");
while (1)
{
channel->timeout = plc->timer;
status = ReadMME (plc, 0, (VS_HOST_ACTION | MMTYPE_IND));
channel->timeout = timer;
if (status < 0)
{
break;
}
if (status > 0)
{
printf ("\n");
if (indicate->MACTION < (sizeof (actions) / sizeof (char const *)))
{
Confirm (plc, "Host Action Request is (%d) %s.", indicate->MACTION, actions [indicate->MACTION]);
}
else
{
error (0, ENOTSUP, "Host Action 0x%0X", indicate->MACTION);
continue;
}
memcpy (channel->peer, indicate->ethernet.OSA, sizeof (channel->peer));
channel->timeout = timer;
if (indicate->MACTION == 0x00)
{
unsigned module = 0;
char firmware [PLC_VERSION_STRING];
if (HostActionResponse (plc))
{
return (-1);
}
if (lseek (plc->PIB.file, 0, SEEK_SET))
{
error (1, errno, FILE_CANTHOME, plc->PIB.name);
}
if (read (plc->PIB.file, &pib_header, sizeof (pib_header)) != sizeof (pib_header))
{
error (1, errno, FILE_CANTREAD, plc->PIB.name);
}
if (lseek (plc->PIB.file, 0, SEEK_SET))
{
error (1, errno, FILE_CANTHOME, plc->PIB.name);
}
if (BE16TOH (*(uint16_t *)(&pib_header)) < 0x0305)
{
offset = LEGACY_PIBOFFSET;
}
else if (BE16TOH (*(uint16_t *)(&pib_header)) < 0x0500)
{
offset = INT6x00_PIBOFFSET;
}
else
{
offset = AR7x00_PIBOFFSET;
}
if (WriteMEM (plc, &plc->PIB, 0, offset, LE16TOH (pib_header.PIBLENGTH)))
{
return (-1);
}
if (lseek (plc->NVM.file, 0, SEEK_SET))
{
error (1, errno, FILE_CANTHOME, plc->NVM.name);
}
if (read (plc->NVM.file, &nvm_header, sizeof (nvm_header)) != sizeof (nvm_header))
{
error (1, errno, FILE_CANTREAD, plc->NVM.name);
}
while (nvm_header.NEXTHEADER)
{
lseek (plc->NVM.file, LE32TOH (nvm_header.NEXTHEADER), SEEK_SET);
if (read (plc->NVM.file, &nvm_header, sizeof (nvm_header)) != sizeof (nvm_header))
{
error (1, errno, FILE_CANTREAD, plc->NVM.name);
}
module++;
}
if (WriteFirmware1 (plc, module, &nvm_header))
{
return (-1);
}
if (StartFirmware1 (plc, module, &nvm_header))
{
return (-1);
}
if (WaitForStart (plc, firmware, sizeof (firmware)))
{
return (-1);
}
if (_anyset (plc->flags, PLC_FLASH_DEVICE))
{
if (WriteNVM (plc))
{
return (-1);
}
if (WritePIB (plc))
{
return (-1);
}
if (FlashNVM (plc))
{
return (-1);
}
}
continue;
}
if (indicate->MACTION == 0x01)
{
if (HostActionResponse (plc))
{
return (-1);
}
close (plc->NVM.file);
if (ReadFirmware1 (plc))
{
return (-1);
}
if ((plc->NVM.file = open (plc->NVM.name = plc->nvm.name, O_BINARY|O_RDONLY)) == -1)
{
error (1, errno, "%s", plc->NVM.name);
}
if (ResetDevice (plc))
{
return (-1);
}
continue;
}
if (indicate->MACTION == 0x02)
{
if (HostActionResponse (plc))
{
return (-1);
}
close (plc->PIB.file);
if (ReadParameters1 (plc))
{
return (-1);
}
if ((plc->PIB.file = open (plc->PIB.name = plc->pib.name, O_BINARY|O_RDONLY)) == -1)
{
error (1, errno, "%s", plc->PIB.name);
}
if (ResetDevice (plc))
{
return (-1);
}
continue;
}
if (indicate->MACTION == 0x03)
{
if (HostActionResponse (plc))
{
return (-1);
}
close (plc->NVM.file);
if (ReadFirmware1 (plc))
{
return (-1);
}
if ((plc->NVM.file = open (plc->NVM.name = plc->nvm.name, O_BINARY|O_RDONLY)) == -1)
{
error (1, errno, "%s", plc->NVM.name);
}
close (plc->PIB.file);
if (ReadParameters1 (plc))
{
return (-1);
}
if ((plc->PIB.file = open (plc->PIB.name = plc->pib.name, O_BINARY|O_RDONLY)) == -1)
{
error (1, errno, "%s", plc->PIB.name);
}
if (ResetDevice (plc))
{
return (-1);
}
continue;
}
if (indicate->MACTION == 0x04)
{
#if 0
/*
* Due to an omission in the INT6300 BootLoader, responding to this VS_HOST_ACTION
* indication will suppress subsequent VS_HOST_ACTION messages and the device will
* not request firmware and parameters; this may be corrected on the INT6400;
*/
if (HostActionResponse (plc))
{
return (-1);
}
#endif
if (WriteCFG (plc))
{
return (-1);
}
/*
* At this point, one could download firmware and parameters without waiting for
* further requests from the device; however, we elect to wait for them since it
* is 'good form'; a device should send code 0x00 within 10 seconds of this one;
*/
continue;
}
if (indicate->MACTION == 0x05)
{
if (HostActionResponse (plc))
{
return (-1);
}
close (plc->NVM.file);
if ((plc->NVM.file = open (plc->NVM.name = NVM, O_BINARY|O_RDONLY)) == -1)
{
error (1, errno, "%s", plc->NVM.name);
}
close (plc->PIB.file);
if ((plc->PIB.file = open (plc->PIB.name = PIB, O_BINARY|O_RDONLY)) == -1)
{
error (1, errno, "%s", plc->PIB.name);
}
if (ResetDevice (plc))
{
return (-1);
}
continue;
}
error (0, ENOSYS, "Host Action 0x%0X", indicate->MACTION);
}
}
return (0);
}
/**
* azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 Data;
UINT8 i;
UINT8 dbEnableAzalia;
UINT8 dbPinRouting;
UINT8 dbChannelNum;
UINT8 dbTempVariable;
UINT16 dwTempVariable;
UINT32 ddBAR0;
UINT32 ddTempVariable;
dbEnableAzalia = 0;
dbChannelNum = 0;
dbTempVariable = 0;
dwTempVariable = 0;
ddBAR0 = 0;
ddTempVariable = 0;
if ( pConfig->AzaliaController == 1 ) {
return;
}
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
if ( ddBAR0 != 0 ) {
if ( ddBAR0 != 0xFFFFFFFF ) {
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
}
}
}
if ( dbEnableAzalia ) {
// Get SDIN Configuration
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
}
// INT#A Azalia resource
Data = 0x93; // Azalia APIC index
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
Data = 0x10; // IRQ16 (INTA#)
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
i = 11;
do {
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable |= BIT0;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
SbStall (1000);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
i--;
} while ((! (dbTempVariable & BIT0)) && (i > 0) );
if ( i == 0 ) {
return;
}
SbStall (1000);
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if ( dwTempVariable & 0x0F ) {
//atleast one azalia codec found
// ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux
//ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting);
dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
do {
if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
// dbChannelNum = 3;
configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
}
dbPinRouting >>= 2;
dbChannelNum++;
} while ( dbChannelNum != 4 );
} else {
//No Azalia codec found
if ( pConfig->AzaliaController != 2 ) {
int StartDevice1 (struct plc * plc)
{
unsigned module = 0;
struct nvm_header1 nvm_header;
struct pib_header pib_header;
uint32_t offset;
if (WriteCFG (plc))
{
return (-1);
}
if (lseek (plc->NVM.file, 0, SEEK_SET))
{
error (PLC_EXIT (plc), errno, FILE_CANTHOME, plc->NVM.name);
return (-1);
}
if (read (plc->NVM.file, &nvm_header, sizeof (nvm_header)) != sizeof (nvm_header))
{
error (PLC_EXIT (plc), errno, FILE_CANTREAD, plc->NVM.name);
return (-1);
}
while (nvm_header.NEXTHEADER)
{
if (lseek (plc->NVM.file, LE32TOH (nvm_header.NEXTHEADER), SEEK_SET) == -1)
{
error (PLC_EXIT (plc), errno, FILE_CANTHOME, plc->NVM.name);
return (-1);
}
if (read (plc->NVM.file, &nvm_header, sizeof (nvm_header)) != sizeof (nvm_header))
{
error (PLC_EXIT (plc), errno, FILE_CANTREAD, plc->NVM.name);
return (-1);
}
module++;
}
if (lseek (plc->PIB.file, 0, SEEK_SET))
{
error (1, errno, FILE_CANTHOME, plc->PIB.name);
}
if (read (plc->PIB.file, &pib_header, sizeof (pib_header)) != sizeof (pib_header))
{
error (1, errno, FILE_CANTREAD, plc->PIB.name);
}
if (lseek (plc->PIB.file, 0, SEEK_SET))
{
error (1, errno, FILE_CANTHOME, plc->PIB.name);
}
if (BE16TOH (*(uint16_t *)(&pib_header)) < 0x0305)
{
offset = LEGACY_PIBOFFSET;
}
else if (BE16TOH (*(uint16_t *)(&pib_header)) < 0x0500)
{
offset = INT6x00_PIBOFFSET;
}
else
{
offset = AR7x00_PIBOFFSET;
}
if (WriteMEM (plc, &plc->PIB, 0, offset, LE16TOH (pib_header.PIBLENGTH)))
{
return (-1);
}
if (WriteFirmware1 (plc, module, &nvm_header))
{
return (-1);
}
if (StartFirmware1 (plc, module, &nvm_header))
{
return (-1);
}
if (lseek (plc->NVM.file, 0, SEEK_SET))
{
error (PLC_EXIT (plc), errno, FILE_CANTHOME, plc->NVM.name);
return (-1);
}
return (0);
}
/**
* azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 Data;
UINT8 i;
UINT8 dbEnableAzalia;
UINT8 dbPinRouting;
UINT8 dbChannelNum;
UINT8 dbTempVariable;
UINT16 dwTempVariable;
UINT32 ddBAR0;
UINT32 ddTempVariable;
dbEnableAzalia = 0;
dbChannelNum = 0;
dbTempVariable = 0;
dwTempVariable = 0;
ddBAR0 = 0;
ddTempVariable = 0;
if ( pConfig->AzaliaController == 1 ) {
return;
}
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
if ( ddBAR0 != 0 ) {
if ( ddBAR0 != 0xFFFFFFFF ) {
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
TRACE ((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
}
}
}
if ( dbEnableAzalia ) {
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 0);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 2);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 4);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 6);
// Get SDIN Configuration
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
}
// INT#A Azalia resource
Data = 0x93; // Azalia APIC index
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
Data = 0x10; // IRQ16 (INTA#)
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
i = 11;
do {
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable |= BIT0;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
SbStall (1000);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
i--;
} while ((! (dbTempVariable & BIT0)) && (i > 0) );
if ( i == 0 ) {
TRACE ((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
return;
}
SbStall (1000);
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if ( dwTempVariable & 0x0F ) {
TRACE ((DMSG_SB_TRACE, "CIMxSB - At least One Azalia CODEC found \n"));
//atleast one azalia codec found
dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
do {
if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
}
dbPinRouting >>= 2;
dbChannelNum++;
} while ( dbChannelNum != 4 );
} else {