int IntcInitFunction(u16 DeviceId, XTmrCtr *TmrInstancePtr, XGpio *GpioInstancePtr, XDmaPs *DmaPtr)
{
XScuGic_Config *IntcConfig;
int status;
// Interrupt controller initialization
IntcConfig = XScuGic_LookupConfig(DeviceId);
status = XScuGic_CfgInitialize(&INTCInst, IntcConfig, IntcConfig->CpuBaseAddress);
if(status != XST_SUCCESS) return XST_FAILURE;
// Call to interrupt setup
status = InterruptSystemSetup(&INTCInst);
if(status != XST_SUCCESS) return XST_FAILURE;
// Connect GPIO interrupt to handler
status = XScuGic_Connect(&INTCInst,
INTC_GPIO_INTERRUPT_ID,
(Xil_ExceptionHandler)BTN_Intr_Handler,
(void *)GpioInstancePtr);
if(status != XST_SUCCESS) return XST_FAILURE;
// Connect timer interrupt to handler
status = XScuGic_Connect(&INTCInst,
INTC_TMR_INTERRUPT_ID,
(Xil_ExceptionHandler)TMR_Intr_Handler,
(void *)TmrInstancePtr);
if(status != XST_SUCCESS) return XST_FAILURE;
// Enable GPIO interrupts interrupt
XGpio_InterruptEnable(GpioInstancePtr, 1);
XGpio_InterruptGlobalEnable(GpioInstancePtr);
// Enable GPIO interrupts in the controller
XScuGic_Enable(&INTCInst, INTC_GPIO_INTERRUPT_ID);
// Enable timer interrupts in the controller
XScuGic_Enable(&INTCInst, INTC_TMR_INTERRUPT_ID);
//Lab7 addition starts here
// Connect DMA interrupt to handler
XScuGic_Connect(&INTCInst,DMA_FAULT_INTR,(Xil_InterruptHandler)XDmaPs_FaultISR,(void *)DmaPtr);
XScuGic_Connect(&INTCInst,DMA_DONE_INTR_0,(Xil_InterruptHandler)XDmaPs_DoneISR_0,(void *)DmaPtr);
// Enable DMA interrupts in the controller
XScuGic_Enable(&INTCInst, DMA_DONE_INTR_0);
//Lab7 addition ends here
return XST_SUCCESS;
}
/******************************************************************************
* @brief Enable External Interrupts
*
* @param None.
*
* @return None.
******************************************************************************/
void Ps7ExtIntrEnable(void)
{
/* Connect device driver handler to be called when interrupt occures */
XScuGic_Connect(&IntcInstance, XPS_FPGA11_INT_ID, (Xil_ExceptionHandler)Ps7ExtIntrHandler, (void *)0);
XScuGic_Connect(&IntcInstance, XPS_FPGA12_INT_ID, (Xil_ExceptionHandler)Ps7ExtIntrHandler, (void *)0);
/* Enable interrupts for the device */
XScuGic_Enable(&IntcInstance, XPS_FPGA11_INT_ID);
XScuGic_Enable(&IntcInstance, XPS_FPGA12_INT_ID);
/* Enable interrupts in the processor */
Xil_ExceptionEnable();
}
/**
*
* This function setups the interrupt system for an Spi device.
* This function is application specific since the actual system may or may not
* have an interrupt controller. The Spi device could be directly connected to
* a processor without an interrupt controller. The user should modify this
* function to fit the application.
*
* @param IntcInstancePtr is a pointer to the instance of the Intc device.
* @param SpiInstancePtr is a pointer to the instance of the Spi device.
* @param SpiIntrId is the interrupt Id for an SPI device.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SpiSetupIntrSystem(XScuGic *IntcInstancePtr,
XSpiPs *SpiInstancePtr, u16 SpiIntrId)
{
int Status;
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */
Xil_ExceptionInit();
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
#endif
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, SpiIntrId,
(Xil_ExceptionHandler)XSpiPs_InterruptHandler,
(void *)SpiInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the Spi device.
*/
XScuGic_Enable(IntcInstancePtr, SpiIntrId);
#ifndef TESTAPP_GEN
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnable();
#endif
return XST_SUCCESS;
}
//////////////////////////// InitializeInterruptSystem////////////////////////////////
int InitializeInterruptSystem(u16 deviceID) {
int Status;
GicConfig = XScuGic_LookupConfig (deviceID);
if(NULL == GicConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, GicConfig, GicConfig->CpuBaseAddress);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = SetUpInterruptSystem(&InterruptController);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XScuGic_Connect (&InterruptController,
XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR,
(Xil_ExceptionHandler) InterruptHandler, NULL);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_Enable(&InterruptController, XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR );
return XST_SUCCESS;
}
static int SetupIntrSystem(XScuGic * IntcInstancePtr, XAxiDma * AxiDmaPtr, u16 TxIntrId)
{
int Status;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,(Xil_InterruptHandler)TxIntrHandler,AxiDmaPtr);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(IntcInstancePtr, TxIntrId);
/* Enable interrupts from the hardware */
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,(void *)IntcInstancePtr);
Xil_ExceptionEnable();
return XST_SUCCESS;
}
int IntcInitFunction(u16 DeviceId, XGpio *GpioInstancePtr)
{
XScuGic_Config *IntcConfig;
int status;
// Interrupt controller initialisation
IntcConfig = XScuGic_LookupConfig(DeviceId);
status = XScuGic_CfgInitialize(&INTCInst, IntcConfig, IntcConfig->CpuBaseAddress);
if(status != XST_SUCCESS) return XST_FAILURE;
// Call to interrupt setup
status = InterruptSystemSetup(&INTCInst);
if(status != XST_SUCCESS) return XST_FAILURE;
// Connect GPIO interrupt to handler
status = XScuGic_Connect(&INTCInst,
INTC_GPIO_INTERRUPT_ID,
(Xil_ExceptionHandler)RF_INTr_Handler,
(void *)GpioInstancePtr);
if(status != XST_SUCCESS) return XST_FAILURE;
// Enable GPIO interrupts interrupt
XGpio_InterruptEnable(GpioInstancePtr, 1);
XGpio_InterruptGlobalEnable(GpioInstancePtr);
// Enable GPIO and timer interrupts in the controller
XScuGic_Enable(&INTCInst, INTC_GPIO_INTERRUPT_ID);
return XST_SUCCESS;
}
int setup_interrupt()
{
//This functions sets up the interrupt on the ARM
int result;
XScuGic_Config *pCfg = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID);
if (pCfg == NULL){
print("Interrupt Configuration Lookup Failed\n\r");
return XST_FAILURE;
}
result = XScuGic_CfgInitialize(&ScuGic,pCfg,pCfg->CpuBaseAddress);
if(result != XST_SUCCESS){
return result;
}
// self test
result = XScuGic_SelfTest(&ScuGic);
if(result != XST_SUCCESS){
return result;
}
// Initialize the exception handler
Xil_ExceptionInit();
// Register the exception handler
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,&ScuGic);
//Enable the exception handler
Xil_ExceptionEnable();
// Connect the Voice Rec ISR to the exception table
result = XScuGic_Connect(&ScuGic,XPAR_FABRIC_VOICEREC_0_INTERRUPT_INTR,(Xil_InterruptHandler)hls_voicerec_isr,&HlsVoiceRec);
if(result != XST_SUCCESS){
return result;
}
// Enable the Voice Rec ISR
XScuGic_Enable(&ScuGic,XPAR_FABRIC_VOICEREC_0_INTERRUPT_INTR);
return XST_SUCCESS;
}
static void init_interrupt()
{
Xil_ExceptionInit();
if ((icconf = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID))
== NULL)
return;
if (XScuGic_CfgInitialize(&ic, icconf, icconf->CpuBaseAddress) !=
XST_SUCCESS)
return;
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler, &ic);
if (XScuGic_Connect(&ic, PL_INT_ID, interrupt_handler,
NULL) != XST_SUCCESS)
return;
XScuGic_SetPriorityTriggerType(&ic, PL_INT_ID, 0, /*highest priority*/
3); /* 3 - rising edge, 1 - active high */
XScuGic_Enable(&ic, PL_INT_ID);
Xil_ExceptionEnable();
}
/*
* This function enables interrupts and connects interrupt service routines declared in
* an interrupt vector table
*/
void fnEnableInterrupts(intc *psIntc, const ivt_t *prgsIvt, unsigned int csIVectors)
{
unsigned int isIVector;
Xil_AssertVoid(psIntc != NULL);
Xil_AssertVoid(psIntc->IsReady == XIL_COMPONENT_IS_READY);
/* Hook up interrupt service routines from IVT */
for (isIVector = 0; isIVector < csIVectors; isIVector++)
{
#ifdef __MICROBLAZE__
XIntc_Connect(psIntc, prgsIvt[isIVector].id, prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef);
/* Enable the interrupt vector at the interrupt controller */
XIntc_Enable(psIntc, prgsIvt[isIVector].id);
#else
XScuGic_SetPriorityTriggerType(psIntc, prgsIvt[isIVector].id, 0xA0, 0x3);
XScuGic_Connect(psIntc, prgsIvt[isIVector].id, prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef);
XScuGic_Enable(psIntc, prgsIvt[isIVector].id);
#endif
}
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, psIntc);
Xil_ExceptionEnable();
}
int zynqMP_r5_gic_initialize() {
#ifndef USE_FREERTOS
u32 Status;
XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&xInterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Register the interrupt handler to the hardware interrupt handling
* logic in the ARM processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,&xInterruptController);
Xil_ExceptionEnable();
#endif
OpenAMPInstPtr.IntrID = VRING1_IPI_INTR_VECT;
XScuGic_Connect(&xInterruptController, VRING1_IPI_INTR_VECT,
(Xil_ExceptionHandler)zynqMP_r5_irq_isr,
&OpenAMPInstPtr);
return 0;
}
static int SetupInterruptSystem(XScuGic *GicInstancePtr, XScuTimer *TimerInstancePtr, u16 TimerIntrId)
{
XScuGic_Config *IntcConfig; //GIC config
Xil_ExceptionInit();
//initialise the GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
//connect to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);
//set up the timer interrupt
XScuGic_Connect(GicInstancePtr, TimerIntrId,
(Xil_ExceptionHandler)TimerIntrHandler,
(void *)TimerInstancePtr);
//enable the interrupt for the Timer at GIC
XScuGic_Enable(GicInstancePtr, TimerIntrId);
//enable interrupt on the timer
XScuTimer_EnableInterrupt(TimerInstancePtr);
// Enable interrupts in the Processor.
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return XST_SUCCESS;
}
int ScuGicExample(u16 DeviceId)
{
int Status;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
GicConfig = XScuGic_LookupConfig(DeviceId);
if (NULL == GicConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, GicConfig,
GicConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform a self-test to ensure that the hardware was built
* correctly
*/
Status = XScuGic_SelfTest(&InterruptController);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Setup the Interrupt System
*/
Status = SetUpInterruptSystem(&InterruptController);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect a device driver handler that will be called when an
* interrupt for the device occurs, the device driver handler performs
* the specific interrupt processing for the device
*/
Status = XScuGic_Connect(&InterruptController, INTC_DEVICE_INT_ID,
(Xil_ExceptionHandler)DeviceDriverHandler,
(void *)&InterruptController);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the device and then cause (simulate) an
* interrupt so the handlers will be called
*/
XScuGic_Enable(&InterruptController, INTC_DEVICE_INT_ID);
return XST_SUCCESS;
}
/**
*
* This function sets up the interrupt system so interrupts can occur for the
* Uart. This function is application-specific. The user should modify this
* function to fit the application.
*
* @param IntcInstancePtr is a pointer to the instance of the INTC.
* @param UartInstancePtr contains a pointer to the instance of the UART
* driver which is going to be connected to the interrupt
* controller.
* @param UartIntrId is the interrupt Id and is typically
* XPAR_<UARTPS_instance>_INTR value from xparameters.h.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
****************************************************************************/
static int SetupInterruptSystem(XScuGic *IntcInstancePtr,
XUartPs *UartInstancePtr,
u16 UartIntrId)
{
int Status;
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig; /* Config for interrupt controller */
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the
* hardware interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler,
IntcInstancePtr);
#endif
/*
* Connect a device driver handler that will be called when an
* interrupt for the device occurs, the device driver handler
* performs the specific interrupt processing for the device
*/
Status = XScuGic_Connect(IntcInstancePtr, UartIntrId,
(Xil_ExceptionHandler) XUartPs_InterruptHandler,
(void *) UartInstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the device
*/
XScuGic_Enable(IntcInstancePtr, UartIntrId);
#ifndef TESTAPP_GEN
/*
* Enable interrupts
*/
Xil_ExceptionEnable();
#endif
return XST_SUCCESS;
}
void vInitialiseTimerForIntQueueTest( void )
{
BaseType_t xStatus;
TmrCntrSetup *pxTimerSettings;
extern XScuGic xInterruptController;
BaseType_t xTimer;
XTtcPs *pxTimerInstance;
XTtcPs_Config *pxTimerConfiguration;
const uint8_t ucRisingEdge = 3;
for( xTimer = 0; xTimer < tmrTIMERS_USED; xTimer++ )
{
/* Look up the timer's configuration. */
pxTimerInstance = &( xTimerInstances[ xTimer ] );
pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
configASSERT( pxTimerConfiguration );
pxTimerSettings = &( xTimerSettings[ xTimer ] );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called
as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( pxTimerInstance );
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
/* The timer frequency is preset in the pxTimerSettings structure.
Derive the values for the other structure members. */
XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( pxTimerInstance );
}
}
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
{
int Status;
XIIC *I2cInstancePtr;
INTC *IntcPtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
IntcPtr = &I2cLibPtr->IntcInstance;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
(Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
I2cInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the IIC device.
*/
XScuGic_Enable(IntcPtr, IIC_INTR_ID);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
/* Enable non-critical exceptions */Xil_ExceptionEnable();
return XST_SUCCESS;
}
/* Complete Interrupt Controller setup, FreeRTOS is doing the pre-init */
static int app_gic_initialize(void)
{
/* Connect Interrupt ID with ISR */
XScuGic_Connect(&xInterruptController, VRING1_IPI_INTR_VECT,
(Xil_ExceptionHandler)bm_env_isr,
(void *)VRING1_IPI_INTR_VECT);
return 0;
}
static void SetupInterruptSystem(XScuGic *GicInstancePtr, u32 *FPGAPtr, u16 FPGAIntrId,
XGpioPs *Gpio, u16 GpioIntrId)
{
XScuGic_Config *IntcConfig; //GIC config
Xil_ExceptionInit();
//initialise the GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
//connect to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);
//set up the timer interrupt
XScuGic_Connect(GicInstancePtr, FPGAIntrId,
(Xil_ExceptionHandler)FPGAIntrHandler,
(void *)FPGAPtr);
//set up the GPIO interrupt
XScuGic_Connect(GicInstancePtr, GpioIntrId,
(Xil_ExceptionHandler)XGpioPs_IntrHandler,
(void *)Gpio);
//Enable interrupts for all the pins in bank 0.
XGpioPs_SetIntrTypePin(Gpio, pbsw, XGPIOPS_IRQ_TYPE_EDGE_RISING);
//Set the handler for gpio interrupts.
XGpioPs_SetCallbackHandler(Gpio, (void *)Gpio, GPIOIntrHandler);
//Enable the GPIO interrupts of Bank 0.
XGpioPs_IntrEnablePin(Gpio, pbsw);
//Enable the interrupt for the GPIO device.
XScuGic_Enable(GicInstancePtr, GpioIntrId);
//enable the interrupt for the Timer at GIC
XScuGic_Enable(GicInstancePtr, FPGAIntrId);
// Enable interrupts in the Processor.
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
printf("Interrupt Set Up\n\r");
}
/**
*
* This function setups the interrupt system such that interrupts can occur
* for the IIC. This function is application specific since the actual
* system may or may not have an interrupt controller. The IIC could be
* directly connected to a processor without an interrupt controller. The
* user should modify this function to fit the application.
*
* @param IicPsPtr contains a pointer to the instance of the Iic
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
*******************************************************************************/
static int SetupInterruptSystem(XIicPs *IicPsPtr)
{
int Status;
XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */
Xil_ExceptionInit();
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
&InterruptController);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(&InterruptController, IIC_INT_VEC_ID,
(Xil_InterruptHandler)XIicPs_MasterInterruptHandler,
(void *)IicPsPtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the Iic device.
*/
XScuGic_Enable(&InterruptController, IIC_INT_VEC_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/**
*
* This function sets up the waveform output timer counter (PWM).
*
* @param None
*
* @return XST_SUCCESS if everything sets up well, XST_FAILURE otherwise.
*
* @note None
*
*****************************************************************************/
int SetupPWM(void)
{
int Status;
TmrCntrSetup *TimerSetup;
XTtcPs *TtcPsPWM;
TimerSetup = &(SettingsTable[TTC_PWM_DEVICE_ID]);
/*
* Set up appropriate options for PWM: interval mode and
* match mode for waveform output.
*/
TimerSetup->Options |= (XTTCPS_OPTION_INTERVAL_MODE |
XTTCPS_OPTION_MATCH_MODE);
/*
* Calling the timer setup routine
* initialize device
* set options
*/
Status = SetupTimer(TTC_PWM_DEVICE_ID);
if(Status != XST_SUCCESS) {
return Status;
}
TtcPsPWM = &(TtcPsInst[TTC_PWM_DEVICE_ID]);
/*
* Connect to the interrupt controller
*/
Status = XScuGic_Connect(&InterruptController, TTC_PWM_INTR_ID,
(Xil_ExceptionHandler)PWMHandler, (void *)&MatchValue);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the Timer counter
*/
XScuGic_Enable(&InterruptController, TTC_PWM_INTR_ID);
/*
* Enable the interrupts for the tick timer/counter
* We only care about the interval timeout.
*/
XTtcPs_EnableInterrupts(TtcPsPWM, XTTCPS_IXR_INTERVAL_MASK);
/*
* Start the tick timer/counter
*/
XTtcPs_Start(TtcPsPWM);
return Status;
}
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Zynq SoC.
*/
void vConfigureTickInterrupt( void )
{
static XScuGic xInterruptController; /* Interrupt controller instance */
BaseType_t xStatus;
extern void FreeRTOS_Tick_Handler( void );
XScuTimer_Config *pxTimerConfig;
XScuGic_Config *pxGICConfig;
const uint8_t ucRisingEdge = 3;
/* This function is called with the IRQ interrupt disabled, and the IRQ
interrupt should be left disabled. It is enabled automatically when the
scheduler is started. */
/* Ensure XScuGic_CfgInitialize() has been called. In this demo it has
already been called from prvSetupHardware() in main(). */
pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID );
xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_SCUTIMER_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge );
/* Install the FreeRTOS tick handler. */
xStatus = XScuGic_Connect( &xInterruptController, XPAR_SCUTIMER_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xTimer );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Initialise the timer. */
pxTimerConfig = XScuTimer_LookupConfig( XPAR_SCUTIMER_DEVICE_ID );
xStatus = XScuTimer_CfgInitialize( &xTimer, pxTimerConfig, pxTimerConfig->BaseAddr );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Enable Auto reload mode. */
XScuTimer_EnableAutoReload( &xTimer );
/* Ensure there is no prescale. */
XScuTimer_SetPrescaler( &xTimer, 0 );
/* Load the timer counter register. */
XScuTimer_LoadTimer( &xTimer, XSCUTIMER_CLOCK_HZ / configTICK_RATE_HZ );
/* Start the timer counter and then wait for it to timeout a number of
times. */
XScuTimer_Start( &xTimer );
/* Enable the interrupt for the xTimer in the interrupt controller. */
XScuGic_Enable( &xInterruptController, XPAR_SCUTIMER_INTR );
/* Enable the interrupt in the xTimer itself. */
vClearTickInterrupt();
XScuTimer_EnableInterrupt( &xTimer );
}
/**
*
* This function sets up the Ticker timer.
*
* @param None
*
* @return XST_SUCCESS if everything sets up well, XST_FAILURE otherwise.
*
* @note None
*
*****************************************************************************/
int SetupTicker(void)
{
int Status;
TmrCntrSetup *TimerSetup;
XTtcPs *TtcPsTick;
TimerSetup = &(SettingsTable[TTC_TICK_DEVICE_ID]);
/*
* Set up appropriate options for Ticker: interval mode without
* waveform output.
*/
TimerSetup->Options |= (XTTCPS_OPTION_INTERVAL_MODE |
XTTCPS_OPTION_WAVE_DISABLE);
/*
* Calling the timer setup routine
* . initialize device
* . set options
*/
Status = SetupTimer(TTC_TICK_DEVICE_ID);
if(Status != XST_SUCCESS) {
return Status;
}
TtcPsTick = &(TtcPsInst[TTC_TICK_DEVICE_ID]);
/*
* Connect to the interrupt controller
*/
Status = XScuGic_Connect(&InterruptController, TTC_TICK_INTR_ID,
(Xil_ExceptionHandler)TickHandler, (void *)TtcPsTick);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the Timer counter
*/
XScuGic_Enable(&InterruptController, TTC_TICK_INTR_ID);
/*
* Enable the interrupts for the tick timer/counter
* We only care about the interval timeout.
*/
XTtcPs_EnableInterrupts(TtcPsTick, XTTCPS_IXR_INTERVAL_MASK);
/*
* Start the tick timer/counter
*/
XTtcPs_Start(TtcPsTick);
return Status;
}
void vdmaIP_Driver_intrInitialize(vdmaIP_DriverInstance *InstancePtr, IntCntrl_t *InterruptController) {
// Interrupt: registering this IP's ISR with the Interrupt Controller passed on by the application developer
int Status = XScuGic_Connect(InterruptController, InstancePtr->intr_id, (Xil_ExceptionHandler) vdmaIP_Driver_ISR, (void *) InstancePtr);
XScuGic_Enable(InterruptController, InstancePtr->intr_id);
if (Status != XST_SUCCESS) {
Xil_AssertVoid(0);
}
}
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Zynq SoC.
*/
void vConfigureTickInterrupt( void )
{
XTtcPs_Config *pxTimerConfig;
BaseType_t xStatus;
XScuGic_Config *pxGICConfig;
static XScuGic xInterruptController; /* Interrupt controller instance */
uint16_t usInterval;
uint8_t ucPrescale = 0;
const uint8_t ucRisingEdge = 3;
/* This function is called with the IRQ interrupt disabled, and the IRQ
interrupt should be left disabled. It is enabled automatically when the
scheduler is started. */
/* Ensure XScuGic_CfgInitialize() has been called. In this demo it has
already been called from prvSetupHardware() in main(). */
pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID );
xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* The interrupt priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, tickINTERRUPT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge );
/* Install the FreeRTOS tick handler. */
xStatus = XScuGic_Connect( &xInterruptController, tickINTERRUPT_ID, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, NULL );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Initialise the Triple Timer Counter (TTC) that is going to be used to
generate the tick interrupt. */
pxTimerConfig = XTtcPs_LookupConfig( tickTTC_ID );
xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfig, pxTimerConfig->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Configure the interval to be the require tick rate. */
XTtcPs_CalcIntervalFromFreq( &xTimerInstance, configTICK_RATE_HZ, &usInterval, &ucPrescale );
XTtcPs_SetInterval( &xTimerInstance, usInterval );
XTtcPs_SetPrescaler( &xTimerInstance, ucPrescale );
/* Interval mode used. */
XTtcPs_SetOptions( &xTimerInstance, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE );
/* Start the timer. */
XTtcPs_Start( &xTimerInstance );
/* Enable the interrupt in the interrupt controller. */
XScuGic_Enable( &xInterruptController, tickINTERRUPT_ID );
/* Enable the interrupt in the timer itself. */
XTtcPs_EnableInterrupts( &xTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
}
/**
* This function sets up the interrupt system for the example. The processing
* contained in this function assumes the hardware system was built with
* and interrupt controller.
*
* @param None.
*
* @return A status indicating XST_SUCCESS or a value that is contained in
* xstatus.h.
*
* @note None.
*
*****************************************************************************/
int zed_ali3_controller_demo_SetupInterruptSystem(zed_ali3_controller_demo_t *pDemo)
{
int Result;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
pDemo->pIntcConfig = XScuGic_LookupConfig(pDemo->uDeviceId_IRQ_Touch);
if (NULL == pDemo->pIntcConfig) {
return XST_FAILURE;
}
Result = XScuGic_CfgInitialize(&(pDemo->Intc), pDemo->pIntcConfig,
pDemo->pIntcConfig->CpuBaseAddress);
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Result = XScuGic_Connect(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch,
(Xil_ExceptionHandler)TouchIsr, pDemo);
if (Result != XST_SUCCESS) {
return Result;
}
/*
* Enable the PS interrupts for the touch controller hardware device.
*/
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler, &(pDemo->Intc));
/* Enable non-critical exceptions */
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/**
*
* This function setups the interrupt system such that interrupts can occur for
* the USB controller. This function is application specific since the actual
* system may or may not have an interrupt controller. The USB controller could
* be directly connected to a processor without an interrupt controller. The
* user should modify this function to fit the application.
*
* @param IntcInstancePtr is a pointer to instance of the Intc controller.
* @param UsbInstancePtr is a pointer to instance of the USB controller.
* @param UsbIntrId is the Interrupt Id and is typically
* XPAR_<INTC_instance>_<USB_instance>_VEC_ID value
* from xparameters.h
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE on error
*
******************************************************************************/
static int UsbSetupIntrSystem(XScuGic *IntcInstancePtr,
XUsbPs *UsbInstancePtr, u16 UsbIntrId)
{
int Status;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Xil_ExceptionInit();
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, UsbIntrId,
(Xil_ExceptionHandler)XUsbPs_IntrHandler,
(void *)UsbInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the device.
*/
XScuGic_Enable(IntcInstancePtr, UsbIntrId);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return XST_SUCCESS;
}
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( uint32_t ulWantedBaud, UBaseType_t uxQueueLength )
{
BaseType_t xStatus;
XUartPs_Config *pxConfig;
/* Create the queue used to hold received characters. NOTE THE COMMENTS AT
THE TOP OF THIS FILE REGARDING THE USE OF QUEUES FOR THIS PURPSOE. */
xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) );
configASSERT( xRxQueue );
/* Create the semaphore used to signal the end of a transmission, then take
the semaphore so it is in the correct state the first time
xSerialSendString() is called. A block time of zero is used when taking
the semaphore as it is guaranteed to be available (it was just created). */
xTxCompleteSemaphore = xSemaphoreCreateBinary();
configASSERT( xTxCompleteSemaphore );
xSemaphoreTake( xTxCompleteSemaphore, 0 );
/* Look up the UART configuration then initialise the dirver. */
pxConfig = XUartPs_LookupConfig( XPAR_XUARTPS_0_DEVICE_ID );
/* Initialise the driver. */
xStatus = XUartPs_CfgInitialize( &xUARTInstance, pxConfig, XPAR_PS7_UART_1_BASEADDR );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Misc. parameter configuration. */
XUartPs_SetBaudRate( &xUARTInstance, ulWantedBaud );
XUartPs_SetOperMode( &xUARTInstance, XUARTPS_OPER_MODE_NORMAL );
/* Install the interrupt service routine that is defined within this
file. */
xStatus = XScuGic_Connect( &xInterruptController, XPAR_XUARTPS_1_INTR, (Xil_ExceptionHandler) prvUART_Handler, (void *) &xUARTInstance );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
/* Ensure interrupts start clear. */
XUartPs_WriteReg( XPAR_PS7_UART_1_BASEADDR, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK );
/* Enable the UART interrupt within the GIC. */
XScuGic_Enable( &xInterruptController, XPAR_XUARTPS_1_INTR );
/* Enable the interrupts of interest in the UART. */
XUartPs_SetInterruptMask( &xUARTInstance, XUARTPS_IXR_RXFULL | XUARTPS_IXR_RXOVR | XUARTPS_IXR_TOUT | XUARTPS_IXR_TXEMPTY );
/* Set the receive timeout. */
XUartPs_SetRecvTimeout( &xUARTInstance, 8 );
return ( xComPortHandle ) 0;
}
void vConfigureTickInterrupt( void )
{
BaseType_t xStatus;
XTtcPs_Config *pxTimerConfiguration;
uint16_t usInterval;
uint8_t ucPrescale;
const uint8_t ucLevelSensitive = 1;
extern XScuGic xInterruptController;
pxTimerConfiguration = XTtcPs_LookupConfig( XPAR_XTTCPS_3_DEVICE_ID );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called as
*xRTOSTickTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( &xRTOSTickTimerInstance );
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( &xRTOSTickTimerInstance, ( XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ) );
/* Derive values from the tick rate. */
XTtcPs_CalcIntervalFromFreq( &xRTOSTickTimerInstance, configTICK_RATE_HZ, &( usInterval ), &( ucPrescale ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( &xRTOSTickTimerInstance, usInterval );
XTtcPs_SetPrescaler( &xRTOSTickTimerInstance, ucPrescale );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_XTTCPS_3_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, XPAR_XTTCPS_3_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xRTOSTickTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, XPAR_XTTCPS_3_INTR );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( &xRTOSTickTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( &xRTOSTickTimerInstance );
}
static int gpio_setupInts(audioPlayer_t *pThis) {
// pointer to driver structure
XScuGic *pGIC;
// get pointer to GIC (already initialized at OS startup
pGIC = prvGetInterruptControllerInstance();
// connect own interrupt handler to GIC handler
XScuGic_Connect(pGIC, GPIO_INTERRUPT_ID,
(Xil_ExceptionHandler) gpio_intrHandler,(void *) pThis);
// Enable interrupt at GIC
XScuGic_Enable(pGIC, GPIO_INTERRUPT_ID);
/* Enable IRQ at core (should be enabled anyway)*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/* Enable IRQ in processor core */
return XST_SUCCESS;
}
int connect_intc_irq() {
int status;
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
status = XScuGic_Connect(&m_gic, PL_INTC_IRQ_ID, (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler, m_axi_intc.CfgPtr->DeviceId);
if (status != XST_SUCCESS)
return status;
/*
* Enable the interrupt for the PL device.
*/
XScuGic_Enable(&m_gic, PL_INTC_IRQ_ID);
return XST_SUCCESS;
}
EN_RESULT SetupInterruptSystem()
{
XScuGic_Config* pInterruptControllerConfig;
// Initialize the exception table.
Xil_ExceptionInit();
// Initialize the interrupt controller driver so that it's ready to use.
pInterruptControllerConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == pInterruptControllerConfig)
{
return EN_ERROR_NULL_POINTER;
}
RETURN_IF_XILINX_CALL_FAILED(XScuGic_CfgInitialize(&g_interruptController,
pInterruptControllerConfig,
pInterruptControllerConfig->CpuBaseAddress),
EN_ERROR_FAILED_TO_INITIALISE_INTERRUPT_CONTROLLER);
// Register the interrupt controller handler with the exception table.
Xil_ExceptionRegisterHandler(
XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &g_interruptController);
// Connect the device driver handler that will be called when an I2C interrupt
// occurs
RETURN_IF_XILINX_CALL_FAILED(XScuGic_Connect(&g_interruptController,
IIC_INTR_ID,
(Xil_InterruptHandler)XIicPs_MasterInterruptHandler,
&g_XIicPsInstance),
EN_ERROR_FAILED_TO_INITIALISE_INTERRUPT_CONTROLLER);
// Enable the interrupts for the IIC device.
XScuGic_Enable(&g_interruptController, IIC_INTR_ID);
// INSERT ANY FURTHER INTERRUPT ENABLES HERE //
// Enable non-critical exceptions.
Xil_ExceptionEnable();
return EN_SUCCESS;
}
