/** * * API to send pullup command to card before using DAT line 3(using 4-bit bus) * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Pullup(XSdPs *InstancePtr) { u32 Status = 0; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * Selects card and sets default block size * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Select_Card (XSdPs *InstancePtr) { u32 Status = 0; /* * Send CMD7 - Select card */ Status = XSdPs_CmdTransfer(InstancePtr, CMD7, InstancePtr->RelCardAddr, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); /* * Set default block size */ Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * Selects card and sets default block size * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ s32 XSdPs_Select_Card (XSdPs *InstancePtr) { s32 Status = 0; /* Send CMD7 - Select card */ Status = XSdPs_CmdTransfer(InstancePtr, CMD7, InstancePtr->RelCardAddr, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } RETURN_PATH: return Status; }
/** * Update Block size for read/write operations. * * @param InstancePtr is a pointer to the instance to be worked on. * @param BlkSize - Block size passed by the user. * * @return None * ******************************************************************************/ int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize) { u32 Status = 0; u32 PresentStateReg = 0; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); if (PresentStateReg & (XSDPS_PSR_INHIBIT_CMD_MASK | XSDPS_PSR_INHIBIT_DAT_MASK | XSDPS_PSR_WR_ACTIVE_MASK | XSDPS_PSR_RD_ACTIVE_MASK)) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Send block write command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); /* * Set block size to the value passed */ BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to get bus width support by card. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param SCR - buffer to store SCR register returned by card. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) { u32 Status = 0; u32 StatusReg = 0x0; u16 BlkCnt; u16 BlkSize; int LoopCnt; #if( ffconfigSDIO_DRIVER_USES_INTERRUPT == 0 ) u32 ulPollCount; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) { SCR[LoopCnt] = 0; } /* * Send block write command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } BlkCnt = XSDPS_SCR_BLKCNT; BlkSize = XSDPS_SCR_BLKSIZE; /* * Set block size to the value passed */ BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Xil_DCacheInvalidateRange( ( unsigned )SCR, 8); Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete */ #if( ffconfigSDIO_DRIVER_USES_INTERRUPT != 0 ) StatusReg = XSdPs_WaitInterrupt( InstancePtr, XSDPS_INTR_ERR_MASK | XSDPS_INTR_TC_MASK ); if( ( StatusReg & XSDPS_INTR_TC_MASK ) != 0 ) { XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; } else { Status = XST_FAILURE; goto RETURN_PATH; } #else /* Limit the time spent here with a simpler counter 'ulPollCount' */ ulPollCount = 0; do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } /* Without some protection the code can easily get stuck here if the card is withdrawn. */ ulPollCount++; if( ulPollCount == POLLCOUNT_MAX ) { Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); #endif /* ffconfigSDIO_DRIVER_USES_INTERRUPT */ XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * Switches the SD card voltage from 3v3 to 1v8 * * * @param InstancePtr is a pointer to the XSdPs instance. * ******************************************************************************/ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) { s32 Status; u16 CtrlReg; u32 ReadReg; /* Send switch voltage command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; } /* Wait for CMD and DATA line to go low */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) { ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); } /* Stop the clock */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, CtrlReg); /* Wait minimum 5mSec */ #if defined (__arm__) || defined (__aarch64__) (void)usleep(5000U); #endif #ifdef __MICROBLAZE__ MB_Sleep(5U); #endif /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); CtrlReg |= XSDPS_HC2_1V8_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); /* Start clock */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Wait for CMD and DATA line to go high */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) { ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); } RETURN_PATH: return Status; }
/** * * Identify type of card using CMD0 + CMD1 sequence * * * @param InstancePtr is a pointer to the XSdPs instance. * ******************************************************************************/ static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) { s32 Status; u32 OperCondReg; u8 ReadReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* 74 CLK delay after card is powered up, before the first command. */ #if defined (__arm__) || defined (__aarch64__) usleep(XSDPS_INIT_DELAY); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif /* CMD0 no response expected */ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Host High Capacity support & High voltage window */ Status = XSdPs_CmdTransfer(InstancePtr, CMD1, XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); if (Status != XST_SUCCESS) { InstancePtr->CardType = XSDPS_CARD_SD; } else { InstancePtr->CardType = XSDPS_CARD_MMC; } XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); /* "Software reset for all" is initiated */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET, XSDPS_SWRST_CMD_LINE_MASK); /* Proceed with initialization only after reset is complete */ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET); while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) { ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET); } Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set bus width to 4-bit in card and host * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusWidth(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef MMC_CARD Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Arg = XSDPS_4_BIT_WIDTH; Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_WIDTH_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #else Arg = XSDPS_MMC_4_BIT_BUS_ARG; Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #ifdef __arm__ usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_WIDTH_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #endif Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; #ifndef MMC_CARD u32 ClockReg; u8 ReadBuff[64]; u16 BlkCnt; u16 BlkSize; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef MMC_CARD BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg); ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK); ClockReg |= XSDPS_CC_SDCLK_FREQ_BASE_MASK | XSDPS_CC_INT_CLK_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg); /* * Wait for internal clock to stabilize */ while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0); /* * Enable SD clock */ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg | XSDPS_CC_SD_CLK_EN_MASK); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #else Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } usleep(XSDPS_MMC_DELAY_FOR_SWITCH); XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #endif Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { s32 Status; u32 StatusReg; u32 Arg; u32 ClockReg; u16 BlkCnt; u16 BlkSize; u8 ReadBuff[64]; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); if (InstancePtr->CardType == XSDPS_CARD_SD) { BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* Change the clock frequency to 50 MHz */ InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else if (InstancePtr->CardType == XSDPS_CARD_MMC) { Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* Change the clock frequency to 52 MHz */ InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else { Arg = XSDPS_MMC_HS200_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* Change the clock frequency to 200 MHz */ InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_Execute_Tuning(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #if defined (__arm__) || defined (__aarch64__) /* Program the Tap delays */ XSdPs_SetTapDelay(InstancePtr); #endif } #if defined (__arm__) || defined (__aarch64__) usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to get bus speed supported by card. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param ReadBuff - buffer to store function group support data * returned by card. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) { s32 Status; u32 StatusReg; u32 Arg; u16 BlkCnt; u16 BlkSize; s32 LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) { ReadBuff[LoopCnt] = 0U; } BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_GET; Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set bus width to 4-bit in card and host * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) { s32 Status; u32 StatusReg; u32 Arg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; Arg = ((u32)InstancePtr->BusWidth); Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else { if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && (InstancePtr->CardType == XSDPS_CHIP_EMMC)) { /* in case of eMMC data width 8-bit */ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; } else { InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; } if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { Arg = XSDPS_MMC_8_BIT_BUS_ARG; } else { Arg = XSDPS_MMC_4_BIT_BUS_ARG; } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Check for transfer complete */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); } #if defined (__arm__) || defined (__aarch64__) usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); /* Width setting in controller */ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { StatusReg |= XSDPS_HC_EXT_BUS_WIDTH; } else { StatusReg |= XSDPS_HC_WIDTH_MASK; } XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set bus width to 4-bit in card and host * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusWidth(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; Arg = InstancePtr->BusWidth; Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else { if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && (InstancePtr->CardType == XSDPS_CHIP_EMMC)) { /* in case of eMMC data width 8-bit */ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; } else { InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; } if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { Arg = XSDPS_MMC_8_BIT_BUS_ARG; } else { Arg = XSDPS_MMC_4_BIT_BUS_ARG; } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } #ifdef __arm__ usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); /* Width setting in controller */ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { StatusReg |= XSDPS_HC_EXT_BUS_WIDTH; } else { StatusReg |= XSDPS_HC_WIDTH_MASK; } XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * Mmc initialization is done in this function * * * @param InstancePtr is a pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful * - XST_FAILURE if failure - could be because * a) MMC is already initialized * b) There is no card inserted * c) One of the steps (commands) in the initialization * cycle failed * @note This function initializes the SD card by following its * initialization and identification state diagram. * CMD0 is sent to reset card. * CMD1 sent to identify voltage and high capacity support * CMD2 and CMD3 are sent to obtain Card ID and * Relative card address respectively. * CMD9 is sent to read the card specific data. * ******************************************************************************/ int XSdPs_MmcCardInitialize(XSdPs *InstancePtr) { u32 PresentStateReg; u32 Status; u32 RespOCR = 0x0; u32 CSD[4]; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* * Check the present state register to make sure * card is inserted and detected by host controller */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0) { Status = XST_FAILURE; goto RETURN_PATH; } /* * 74 CLK delay after card is powered up, before the first command. */ #ifdef __arm__ usleep(XSDPS_INIT_DELAY); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif /* * CMD0 no response expected */ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } RespOCR = 0; /* * Send CMD1 while card is still busy with power up */ while ((RespOCR & XSDPS_RESPOCR_READY) == 0) { /* * Host High Capacity support & High volage window */ Status = XSdPs_CmdTransfer(InstancePtr, CMD1, XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Response with card capacity */ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); } /* * Update HCS support flag based on card capacity response */ if (RespOCR & XSDPS_ACMD41_HCS) InstancePtr->HCS = 1; /* * CMD2 for Card ID */ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } InstancePtr->CardID[0] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); InstancePtr->CardID[1] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP1_OFFSET); InstancePtr->CardID[2] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP2_OFFSET); InstancePtr->CardID[3] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Relative card address is stored as the upper 16 bits * This is to avoid shifting when sending commands */ InstancePtr->RelCardAddr = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET) & 0xFFFF0000; Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Card specific data is read. * Currently not used for any operation. */ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP1_OFFSET); CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP2_OFFSET); CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; #if( ffconfigSDIO_DRIVER_USES_INTERRUPT == 0 ) u32 ulPollCount; #endif #ifndef MMC_CARD /* u32 ClockReg; */ #ifdef __ICCARM__ #pragma data_alignment = 32 u8 ReadBuff[64]; #pragma data_alignment = 4 #else u8 ReadBuff[64] __attribute__ ((aligned(32))); #endif u16 BlkCnt; u16 BlkSize; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef MMC_CARD BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheFlushRange( ( unsigned )ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #if( ffconfigSDIO_DRIVER_USES_INTERRUPT != 0 ) StatusReg = XSdPs_WaitInterrupt( InstancePtr, XSDPS_INTR_ERR_MASK | XSDPS_INTR_TC_MASK ); if( ( StatusReg & XSDPS_INTR_TC_MASK ) != 0 ) { Status = XST_SUCCESS; } else { Status = XST_FAILURE; goto RETURN_PATH; } #else /* * Check for transfer complete * Polling for response * Limit the time spent here with a simpler counter 'ulPollCount' */ ulPollCount = 0; do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } ulPollCount++; if( ulPollCount == POLLCOUNT_MAX ) { Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); #endif /* ffconfigSDIO_DRIVER_USES_INTERRUPT */ /* * Change the clock frequency to 50 MHz */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #else Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #ifdef __arm__ usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #endif Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to get EXT_CSD register of eMMC. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param ReadBuff - buffer to store EXT_CSD * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; u16 BlkCnt; u16 BlkSize; int LoopCnt; #if( ffconfigSDIO_DRIVER_USES_INTERRUPT == 0 ) u32 ulPollCount; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) { ReadBuff[LoopCnt] = 0; } BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT; BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheInvalidateRange( ( unsigned )ReadBuff, 512); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = 0; /* * Send SEND_EXT_CSD command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #if( ffconfigSDIO_DRIVER_USES_INTERRUPT != 0 ) StatusReg = XSdPs_WaitInterrupt( InstancePtr, XSDPS_INTR_ERR_MASK | XSDPS_INTR_TC_MASK ); if( ( StatusReg & XSDPS_INTR_TC_MASK ) != 0 ) { Status = XST_SUCCESS; } else { Status = XST_FAILURE; } #else /* * Check for transfer complete * Polling for response for now * Limit the time spent here with a simpler counter 'ulPollCount' */ ulPollCount = 0; do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } ulPollCount++; if( ulPollCount == POLLCOUNT_MAX ) { Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); #endif /* ffconfigSDIO_DRIVER_USES_INTERRUPT */ XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * This function performs SD write in polled mode. * * @param InstancePtr is a pointer to the instance to be worked on. * @param Arg is the address passed by the user that is to be sent as * argument along with the command. * @param BlkCnt - Block count passed by the user. * @param Buff - Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if initialization was successful * - XST_FAILURE if failure - could be because another transfer * is in progress or command or data inhibit is set * ******************************************************************************/ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) { s32 Status; u32 PresentStateReg; u32 StatusReg; if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) != XSDPS_CAPS_EMB_SLOT)) { if(InstancePtr->Config.CardDetect != 0U) { /* Check status to ensure card is initialized */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) { Status = XST_FAILURE; goto RETURN_PATH; } } } /* Set block size to 512 if not already set */ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) { Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK); /* Send block write command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to get bus width support by card. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param SCR - buffer to store SCR register returned by card. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) { u32 Status = 0; u32 StatusReg = 0x0; u16 BlkCnt; u16 BlkSize; int LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) { SCR[LoopCnt] = 0; } /* * Send block write command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } BlkCnt = XSDPS_SCR_BLKCNT; BlkSize = XSDPS_SCR_BLKSIZE; /* * Set block size to the value passed */ BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Xil_DCacheInvalidateRange(SCR, 8); Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * Mmc initialization is done in this function * * * @param InstancePtr is a pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful * - XST_FAILURE if failure - could be because * a) MMC is already initialized * b) There is no card inserted * c) One of the steps (commands) in the initialization * cycle failed * @note This function initializes the SD card by following its * initialization and identification state diagram. * CMD0 is sent to reset card. * CMD1 sent to identify voltage and high capacity support * CMD2 and CMD3 are sent to obtain Card ID and * Relative card address respectively. * CMD9 is sent to read the card specific data. * ******************************************************************************/ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) { u32 PresentStateReg; s32 Status; u32 RespOCR; u32 CSD[4]; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) != XSDPS_CAPS_EMB_SLOT)) { if(InstancePtr->Config.CardDetect != 0U) { /* * Check the present state register to make sure * card is inserted and detected by host controller */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } } } /* CMD0 no response expected */ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } RespOCR = 0U; /* Send CMD1 while card is still busy with power up */ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) { /* Host High Capacity support & High volage window */ Status = XSdPs_CmdTransfer(InstancePtr, CMD1, XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Response with card capacity */ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); } /* Update HCS support flag based on card capacity response */ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) { InstancePtr->HCS = 1U; } /* CMD2 for Card ID */ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } InstancePtr->CardID[0] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); InstancePtr->CardID[1] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP1_OFFSET); InstancePtr->CardID[2] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP2_OFFSET); InstancePtr->CardID[3] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); /* Set relative card address */ InstancePtr->RelCardAddr = 0x12340000U; Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Card specific data is read. * Currently not used for any operation. */ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP1_OFFSET); CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP2_OFFSET); CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); InstancePtr->Card_Version = (CSD[3] & CSD_SPEC_VER_MASK) >>18U; Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; #ifndef MMC_CARD u32 ClockReg; u8 ReadBuff[64]; u16 BlkCnt; u16 BlkSize; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef MMC_CARD BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheInvalidateRange(ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* * Change the clock frequency to 50 MHz */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #else Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #ifdef __arm__ usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #endif Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * SD initialization is done in this function * * * @param InstancePtr is a pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful * - XST_FAILURE if failure - could be because * a) SD is already initialized * b) There is no card inserted * c) One of the steps (commands) in the initialization cycle failed * * @note This function initializes the SD card by following its * initialization and identification state diagram. * CMD0 is sent to reset card. * CMD8 and ACDM41 are sent to identify voltage and * high capacity support * CMD2 and CMD3 are sent to obtain Card ID and * Relative card address respectively. * CMD9 is sent to read the card specific data. * ******************************************************************************/ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) { u32 PresentStateReg; s32 Status; u32 RespOCR; u32 CSD[4]; u32 Arg; u8 ReadReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) != XSDPS_CAPS_EMB_SLOT)) { if(InstancePtr->Config.CardDetect != 0U) { /* * Check the present state register to make sure * card is inserted and detected by host controller */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } } } /* CMD0 no response expected */ Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * CMD8; response expected * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, XSDPS_CMD8_VOL_PATTERN, 0U); if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) { Status = XST_FAILURE; goto RETURN_PATH; } if (Status == XSDPS_CT_ERROR) { /* "Software reset for all" is initiated */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET, XSDPS_SWRST_CMD_LINE_MASK); /* Proceed with initialization only after reset is complete */ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET); while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) { ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET); } } RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); if (RespOCR != XSDPS_CMD8_VOL_PATTERN) { InstancePtr->Card_Version = XSDPS_SD_VER_1_0; } else { InstancePtr->Card_Version = XSDPS_SD_VER_2_0; } RespOCR = 0U; /* Send ACMD41 while card is still busy with power up */ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { Arg |= XSDPS_OCR_S18; } /* 0x40300000 - Host High Capacity support & 3.3V window */ Status = XSdPs_CmdTransfer(InstancePtr, ACMD41, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Response with card capacity */ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); } /* Update HCS support flag based on card capacity response */ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) { InstancePtr->HCS = 1U; } /* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */ #ifndef UHS_BROKEN if ((RespOCR & XSDPS_OCR_S18) != 0U) { InstancePtr->Switch1v8 = 1U; Status = XSdPs_Switch_Voltage(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } #endif /* CMD2 for Card ID */ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } InstancePtr->CardID[0] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); InstancePtr->CardID[1] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP1_OFFSET); InstancePtr->CardID[2] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP2_OFFSET); InstancePtr->CardID[3] = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); do { Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Relative card address is stored as the upper 16 bits * This is to avoid shifting when sending commands */ InstancePtr->RelCardAddr = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET) & 0xFFFF0000U; } while (InstancePtr->RelCardAddr == 0U); Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Card specific data is read. * Currently not used for any operation. */ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP1_OFFSET); CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP2_OFFSET); CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to get EXT_CSD register of eMMC. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param ReadBuff - buffer to store EXT_CSD * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; u16 BlkCnt; u16 BlkSize; int LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) { ReadBuff[LoopCnt] = 0; } BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT; BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheInvalidateRange(ReadBuff, 512); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = 0; /* * Send SEND_EXT_CSD command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * This function performs SD read in polled mode. * * @param InstancePtr is a pointer to the instance to be worked on. * @param Arg is the address passed by the user that is to be sent as * argument along with the command. * @param BlkCnt - Block count passed by the user. * @param Buff - Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if initialization was successful * - XST_FAILURE if failure - could be because another transfer * is in progress or command or data inhibit is set * ******************************************************************************/ int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) { u32 Status; u32 PresentStateReg; u32 StatusReg; /* * Check status to ensure card is initialized */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Set block size to 512 if not already set */ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) { Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK); Xil_DCacheInvalidateRange(Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); /* * Send block read command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }