int wl_timer_initialize(){
int status = 0;
XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
XTmrCtr_Config *TmrCtrConfigPtr;
//Initialize the timer counter
status = XTmrCtr_Initialize(TmrCtrInstancePtr, TMRCTR_DEVICE_ID);
if (status == XST_DEVICE_IS_STARTED) {
xil_printf("Timer was already running; clear/init manually\n");
TmrCtrConfigPtr = XTmrCtr_LookupConfig(TMRCTR_DEVICE_ID);
TmrCtrInstancePtr->BaseAddress = TmrCtrConfigPtr->BaseAddress;
TmrCtrInstancePtr->IsReady = XIL_COMPONENT_IS_READY;
XTmrCtr_Stop(TmrCtrInstancePtr, 0);
XTmrCtr_Reset(TmrCtrInstancePtr, 0);
status = XTmrCtr_Initialize(TmrCtrInstancePtr, TMRCTR_DEVICE_ID);
}
if (status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in XtmrCtr_Initialize (%d)\n", status);
}
// Set timer 0 to into a "count down" mode
XTmrCtr_SetOptions(TmrCtrInstancePtr, 0, (XTC_DOWN_COUNT_OPTION));
///Timer Setup///
XTmrCtr_SetResetValue(TmrCtrInstancePtr,1,0); //Sets it so issuing a "start" command begins at counter=0
/////////////////
return status;
}
void timer_setstate(XTmrCtr *timer, char state) {
// Enable / disable timer
if(state) {
XTmrCtr_Start(timer, 0);
} else {
XTmrCtr_Stop(timer, 0);
}
}
void timer_stop(uint32_t *elapsedTime) {
if (!initialized || !started) return;
XTmrCtr_Stop(&TmrCtrInstancePtr, 0);
stopTime = XTmrCtr_GetValue(&TmrCtrInstancePtr, 0);
*elapsedTime = (stopTime - startTime);
started = false;
}
void Timer_InterruptHandler(void *data, u8 TmrCtrNumber)
{
print("\r\n");
print("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r\n");
print(" Inside Timer ISR \n \r ");
XTmrCtr_Stop(&TimerInstancePtr,TmrCtrNumber);
XGpioPs_WritePin(&psGpioInstancePtr,iPinNumber,0);
XGpioPs_WritePin(&psGpioInstancePtr,55,0);
XTmrCtr_Reset(&TimerInstancePtr,TmrCtrNumber);
print(" Timer ISR Exit\n \n \r");
print("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r\n");
}
/* This is an application defined callback function used to install the tick
interrupt handler. It is provided as an application callback because the kernel
will run on lots of different MicroBlaze and FPGA configurations - not all of
which will have the same timer peripherals defined or available. This example
uses the AXI Timer 0. If that is available on your hardware platform then this
example callback implementation should not require modification. The name of
the interrupt handler that should be installed is vPortTickISR(), which the
function below declares as an extern. */
void vApplicationSetupTimerInterrupt( void )
{
portBASE_TYPE xStatus;
const unsigned char ucTimerCounterNumber = ( unsigned char ) 0U;
const unsigned long ulCounterValue = ( ( TIMER_CLOCK_FREQ / configTICK_RATE_HZ ) - 1UL );
extern void vPortTickISR( void *pvUnused );
/* Initialise the timer/counter. */
xStatus = XTmrCtr_Initialize( &xTimer0Instance, TIMER_DEVICE_ID );
if (xStatus == XST_DEVICE_IS_STARTED)
{
xTimer0Instance.IsReady = XIL_COMPONENT_IS_READY;
XTmrCtr_Stop( &xTimer0Instance, TIMER_DEVICE_ID );
XTmrCtr_Reset( &xTimer0Instance, TIMER_DEVICE_ID );
xStatus = XTmrCtr_Initialize( &xTimer0Instance, TIMER_DEVICE_ID );
xStatus = XST_SUCCESS;
}
if( xStatus == XST_SUCCESS )
{
/* Install the tick interrupt handler as the timer ISR.
*NOTE* The xPortInstallInterruptHandler() API function must be used for
this purpose. */
xStatus = xPortInstallInterruptHandler(TIMER_INTR_ID, vPortTickISR, NULL );
}
if( xStatus == pdPASS )
{
/* Enable the timer interrupt in the interrupt controller.
*NOTE* The vPortEnableInterrupt() API function must be used for this
purpose. */
vPortEnableInterrupt(TIMER_INTR_ID);
/* Configure the timer interrupt handler. */
XTmrCtr_SetHandler( &xTimer0Instance, ( void * ) vPortTickISR, NULL );
/* Set the correct period for the timer. */
XTmrCtr_SetResetValue( &xTimer0Instance, ucTimerCounterNumber, ulCounterValue );
/* Enable the interrupts. Auto-reload mode is used to generate a
periodic tick. Note that interrupts are disabled when this function is
called, so interrupts will not start to be processed until the first
task has started to run. */
XTmrCtr_SetOptions( &xTimer0Instance, ucTimerCounterNumber, ( XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_DOWN_COUNT_OPTION ) );
/* Start the timer. */
XTmrCtr_Start( &xTimer0Instance, ucTimerCounterNumber );
}
/* Sanity check that the function executed as expected. */
configASSERT( ( xStatus == pdPASS ) );
}
/**
*
* This function is used to override the driver's default sleep functionality.
* For MicroBlaze systems, the XDpRxSs_WaitUs driver function's default behavior
* is to use the MB_Sleep function from microblaze_sleep.h, which is implemented
* in software and only has millisecond accuracy. For this reason, using a
* hardware timer is preferable. For ARM/Zynq SoC systems, the SoC's timer is
* used - XDpRxSs_WaitUs will ignore this custom timer handler.
*
* @param InstancePtr is a pointer to the XDpRxSs core instance.
* @param MicroSeconds is the number of microseconds to delay/sleep for.
*
* @return None.
*
* @note Use the XDpRxSs_SetUserTimerHandler driver function to set this
* function as the handler for when the XDpRxSs_WaitUs driver
* function is called.
*
******************************************************************************/
void DpRxSs_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
{
XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;
u32 TimerVal;
XTmrCtr_Start(DpRxSsPtr->DpPtr->UserTimerPtr, 0);
/* Wait specified number of useconds. */
do {
TimerVal = XTmrCtr_GetValue(DpRxSsPtr->DpPtr->UserTimerPtr, 0);
} while (TimerVal < (MicroSeconds *
(DpRxSsPtr->DpPtr->Config.SAxiClkHz / 1000000)));
XTmrCtr_Stop(DpRxSsPtr->DpPtr->UserTimerPtr, 0);
}
/*
* Timer Interrupt Handler
*/
void tmrIntrHandler(void *InstancePtr) {
if (XTmrCtr_IsExpired(&tmrCtr, 0)) {
//Stop Timer Controller
XTmrCtr_Stop(&tmrCtr, 0);
//Set flag
tmrExpired = BOOL_TRUE;
//Reset Timer Controller
XTmrCtr_Reset(&tmrCtr, 0);
//Start Timer
XTmrCtr_Start(&tmrCtr, 0);
}
}
int main (void) {
int old_count = 0;
gpio_init();
XGpio_DiscreteWrite(&led,1,0);
XGpio_DiscreteWrite(&ledPush,1,0x1);
xil_printf("-- Entering main() --\r\n");
XTmrCtr_Initialize(&XTC, XPAR_OPB_TIMER_1_DEVICE_ID );
XTmrCtr_SetOptions(&XTC, 0, XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION |
XTC_AUTO_RELOAD_OPTION );
XTmrCtr_SetHandler(&XTC, TimerCounterHandler, &XTC);
microblaze_register_handler( (XInterruptHandler)XTmrCtr_InterruptHandler,
&XTC );
microblaze_enable_interrupts();
XTmrCtr_SetResetValue ( &XTC, 0, 50*1000000L );
XTmrCtr_Start( &XTC, 0 );
XGpio_DiscreteWrite(&ledPush,1,0x3);
while(1) {
if (gpio_check()) break;
if ( old_count != intr_count ) {
xil_printf(" TmrCtr update %d\r\n", intr_count );
XGpio_DiscreteWrite(&led,1,3);
XGpio_DiscreteWrite(&ledPush,1,0x10 | (intr_count&0xF));
old_count = intr_count;
}
}
if ( XTmrCtr_IsExpired( &XTC, 0 ) ) {
xil_printf(" TmrCtr Timed out\r\n" );
} else {
xil_printf(" TmrCtr un-Timeout\r\n" );
}
XTmrCtr_Stop(&XTC, 0 );
microblaze_disable_interrupts();
XGpio_DiscreteWrite(&ledPush,1,0x10);
xil_printf("-- Exiting main() --\r\n");
return 0;
}
/**
* This function is the handler which performs processing for the timer counter.
* It is called from an interrupt context such that the amount of processing
* performed should be minimized. It is called when the timer counter expires
* if interrupts are enabled.
*
* This handler provides an example of how to handle timer counter interrupts
* but is application specific.
*
* @param CallBackRef is a pointer to the callback function
* @param TmrCtrNumber is the number of the timer to which this
* handler is associated with.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber)
{
static int state;
static int upc = 0;
static int cnt = 0;
static int range = 255;
static int time_vals[Nc] = {0};
static u8 char_vals[Nc] = {0};
static int qs[3] = {16, 40, 66};
int val;
/* LED Blink */
int *LED = (int *)XPAR_GPIO_0_BASEADDR;
static int led_value = 1;
led_value ^= 1;
*LED = led_value;
/* Character generator */
upc++;
switch(state) {
case 0:
cnt++;
//xil_printf("%d\r\n", cnt);
char_vals[cnt] = (u8) (rand() % (range + 1));
xil_printf("%d\r\n", char_vals[cnt]);
time_vals[cnt] = upc;
if (cnt!=Nc){
state = 1;
}
else{
xil_printf("END\r\n");
XTmrCtr_Stop((XTmrCtr *)CallBackRef, TmrCtrNumber);
}
break;
case 1:
val = rand() % 100;
if (val>qs[0]){
state = 2;
}
else{
state = 0;
}
break;
case 2:
val = rand() % 100;
if (val>qs[1]){
state = 3;
}
else{
state = 0;
}
break;
case 3:
state = 4;
break;
case 4:
val = rand() % 100;
if (val>qs[2]){
state = 5;
}
else{
state = 0;
}
break;
case 5:
state = 0;
break;
default:
state = 0;
}
}
/**
* This function does a minimal test on the timer counter device and driver as a
* design example. The purpose of this function is to illustrate how to use the
* XTmrCtr component. It initializes a timer counter and then sets it up in
* compare mode with auto reload such that a periodic interrupt is generated.
*
* This function uses interrupt driven mode of the timer counter.
*
* @param IntcInstancePtr is a pointer to the Interrupt Controller
* driver Instance
* @param TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance
* @param DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
* xparameters.h
* @param IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
* value from xparameters.h
* @param TmrCtrNumber is the number of the timer to which this
* handler is associated with.
*
* @return
* - XST_SUCCESS if the Test is successful
* - XST_FAILURE if the Test is not successful
*
* @note This function contains an infinite loop such that if interrupts
* are not working it may never return.
*
*****************************************************************************/
int TmrCtrFastIntrExample(XIntc* IntcInstancePtr,
XTmrCtr* TmrCtrInstancePtr,
u16 DeviceId,
u16 IntrId,
u8 TmrCtrNumber)
{
int Status;
int LastTimerExpired = 0;
/*
* Initialize the timer counter so that it's ready to use,
* specify the device ID that is generated in xparameters.h
*/
Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform a self-test to ensure that the hardware was built
* correctly, use the 1st timer in the device (0)
*/
Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the timer counter to the interrupt subsystem such that
* interrupts can occur. This function is application specific.
*/
Status = TmrCtrSetupIntrSystem(IntcInstancePtr,
TmrCtrInstancePtr,
DeviceId,
IntrId,
TmrCtrNumber);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Setup the handler for the timer counter that will be called from the
* interrupt context when the timer expires, specify a pointer to the
* timer counter driver instance as the callback reference so the
* handler is able to access the instance data
*/
XTmrCtr_SetHandler(TmrCtrInstancePtr, TimerCounterHandler,
TmrCtrInstancePtr);
/*
* Enable the interrupt of the timer counter so interrupts will occur
* and use auto reload mode such that the timer counter will reload
* itself automatically and continue repeatedly, without this option
* it would expire once only
*/
XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber,
XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION);
/*
* Set a reset value for the timer counter such that it will expire
* eariler than letting it roll over from 0, the reset value is loaded
* into the timer counter when it is started
*/
XTmrCtr_SetResetValue(TmrCtrInstancePtr, TmrCtrNumber, RESET_VALUE);
/*
* Start the timer counter such that it's incrementing by default,
* then wait for it to timeout a number of times
*/
XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber);
while (1) {
/*
* Wait for the first timer counter to expire as indicated by
* the shared variable which the handler will increment
*/
while (TimerExpired == LastTimerExpired) {
}
LastTimerExpired = TimerExpired;
/*
* If it has expired a number of times, then stop the timer
* counter and stop this example
*/
if (TimerExpired == 3) {
XTmrCtr_Stop(TmrCtrInstancePtr, TmrCtrNumber);
break;
}
}
TmrCtrDisableIntr(IntcInstancePtr, DeviceId);
return XST_SUCCESS;
}
int main (void)
{
float u[n*n], v[n*n], u0[n*n], v0[n*n];
float x, y, x0, y_0, f, r, U[2], V[2], s, t;
int i, j, i0, j_0, i1, j_1,m;
int k;
float visc=1.25;
float dt=2.36;
int start,end;
xil_printf("----------------------- START ------------------------ ! \n\r");
int MASK_LENGTH= 10;//(int) ceil((log(BUFFER_SIZE))/log(2));
int MASK = ((1 << MASK_LENGTH)-1);
//-- Flag Initializations
for (i=0; i<BUFFER_SIZE; i++)
{
flag1[i]=0;
flag2[i]=0;
flag3[i]=0;
}
XTmrCtr timer;
XTmrCtr_Initialize(&timer, XPAR_XPS_TIMER_0_DEVICE_ID);
XTmrCtr_Reset(&timer, TIMER_COUNTER_0);
start = XTmrCtr_GetValue(&timer, TIMER_COUNTER_0);
// Start timer
XTmrCtr_Start(&timer, TIMER_COUNTER_0);
//------- LOOP FOR IMAGES -------
for (k=0; k < Number_of_Images; k++) // loop for Images
{
consumer_index = ci; // for nested loop can be i*n+j
while (consumer_index<SIZE_floid)
{
if (read_from_fifo ==1)
{
getfsl(fifo_index,0);
if (fifo_index!=999999999)
{
getfsl(fifo_data,0);
getfsl(fifo_data2,0);
xil_printf("READ %d FROM FIFO \t",fifo_index);
if (consumer_index == fifo_index && fifo_index!=999999999)
{
// consume the data directly
consumer_data = fifo_data;
consumer_data2 = fifo_data2;
xil_printf("»»»»»»»»»»»»»»»»»»»»»»»»»»»»»»»»» %d DIRECTLY CONSUMED !\n\r",consumer_index);
consumer_index=consumer_index+1;//ci;
consumer_done=1;
read_from_fifo=1;
//-- The rest of consumer's computing stage here : output: consumer_index
u0[i+(n+2)*j] = consumer_data; // u[i+n*j]
v0[i+(n+2)*j] = consumer_data2; // v[i+n*j]
y = j<=n/2 ? j : j-n;
r = x*x+y*y;
if ( r==0.0 ) continue;
f = exp(-r*dt*visc);
U[0] = u0[i +(n+2)*j];
V[0] = v0[i +(n+2)*j];
U[1] = u0[i+1+(n+2)*j];
V[1] = v0[i+1+(n+2)*j];
u0[i +(n+2)*j] = f*( (1-x*x/r)*U[0] -x*y/r *V[0] );
u0[i+1+(n+2)*j] = f*( (1-x*x/r)*U[1] -x*y/r *V[1] );
v0[i+ (n+2)*j] = f*( -y*x/r *U[0] + (1-y*y/r)*V[0] );
v0[i+1+(n+2)*j] = f*( -y*x/r *U[1] + (1-y*y/r)*V[1] );
}
}
else if (fifo_index==999999999)
{
xil_printf("==PRODUCER STOPPED AND consumer_index IS %d!\n\r",consumer_index);
read_from_fifo=0;
//consumer_index++;
}
}
// compute the hash
consumer_hash_index = consumer_index & MASK; // here index is not refreshing
fifo_hash_index = fifo_index & MASK;
// Load from memory
if (flag1[consumer_hash_index]==1 && index1[consumer_hash_index]==consumer_index)
{
flag1[consumer_hash_index]=0;
consumer_data= data1[consumer_hash_index];
xil_printf("========== LOAD consumer_index %d from T1 ================!\n\r",consumer_index);
consumer_index++;
consumer_done=1;
//-- The rest of consumer's computing stage here : output: consumer_index
u0[i+(n+2)*j] = consumer_data; // u[i+n*j]
v0[i+(n+2)*j] = consumer_data2; // v[i+n*j]
y = j<=n/2 ? j : j-n;
r = x*x+y*y;
if ( r==0.0 ) continue;
f = exp(-r*dt*visc);
U[0] = u0[i +(n+2)*j];
V[0] = v0[i +(n+2)*j];
U[1] = u0[i+1+(n+2)*j];
V[1] = v0[i+1+(n+2)*j];
u0[i +(n+2)*j] = f*( (1-x*x/r)*U[0] -x*y/r *V[0] );
u0[i+1+(n+2)*j] = f*( (1-x*x/r)*U[1] -x*y/r *V[1] );
v0[i+ (n+2)*j] = f*( -y*x/r *U[0] + (1-y*y/r)*V[0] );
v0[i+1+(n+2)*j] = f*( -y*x/r *U[1] + (1-y*y/r)*V[1] );
if (fifo_index!=999999999)
read_from_fifo=1;
}
else if (flag2[consumer_hash_index]==1 && index2[consumer_hash_index]==consumer_index)
{
flag2[consumer_hash_index]=0;
consumer_data= data2[consumer_hash_index];
consumer_index++;
read_from_fifo=1;
consumer_done=1;
xil_printf("=================== LOAD consumer_index %d from T2 ================!\n\r",consumer_index);
//-- The rest of consumer's computing stage here : output: consumer_index
u0[i+(n+2)*j] = consumer_data; // u[i+n*j]
v0[i+(n+2)*j] = consumer_data2; // v[i+n*j]
y = j<=n/2 ? j : j-n;
r = x*x+y*y;
if ( r==0.0 ) continue;
f = exp(-r*dt*visc);
U[0] = u0[i +(n+2)*j];
V[0] = v0[i +(n+2)*j];
U[1] = u0[i+1+(n+2)*j];
V[1] = v0[i+1+(n+2)*j];
u0[i +(n+2)*j] = f*( (1-x*x/r)*U[0] -x*y/r *V[0] );
u0[i+1+(n+2)*j] = f*( (1-x*x/r)*U[1] -x*y/r *V[1] );
v0[i+ (n+2)*j] = f*( -y*x/r *U[0] + (1-y*y/r)*V[0] );
v0[i+1+(n+2)*j] = f*( -y*x/r *U[1] + (1-y*y/r)*V[1] );
}
else if (flag3[consumer_hash_index]==1 && index3[consumer_hash_index]==consumer_index)
{
flag3[consumer_hash_index]=0;
consumer_data= data3[consumer_hash_index];
consumer_index++;
read_from_fifo=1;
consumer_done=1;
consumer_done=1;
xil_printf("=================== LOAD consumer_index %d from T3 ================!\n\r",consumer_index);
//-- The rest of consumer's computing stage here : output: consumer_index
u0[i+(n+2)*j] = consumer_data; // u[i+n*j]
v0[i+(n+2)*j] = consumer_data2; // v[i+n*j]
y = j<=n/2 ? j : j-n;
r = x*x+y*y;
if ( r==0.0 ) continue;
f = exp(-r*dt*visc);
U[0] = u0[i +(n+2)*j];
V[0] = v0[i +(n+2)*j];
U[1] = u0[i+1+(n+2)*j];
V[1] = v0[i+1+(n+2)*j];
u0[i +(n+2)*j] = f*( (1-x*x/r)*U[0] -x*y/r *V[0] );
u0[i+1+(n+2)*j] = f*( (1-x*x/r)*U[1] -x*y/r *V[1] );
v0[i+ (n+2)*j] = f*( -y*x/r *U[0] + (1-y*y/r)*V[0] );
v0[i+1+(n+2)*j] = f*( -y*x/r *U[1] + (1-y*y/r)*V[1] );
}
// Store in memory
else if (read_from_fifo ==1 && consumer_done==0)
{
if (flag1[fifo_hash_index]==0 && fifo_index!=999999999)
{
data1[fifo_hash_index] =fifo_data;
index1[fifo_hash_index] =fifo_index;
flag1[fifo_hash_index]=1;
read_from_fifo=1;
xil_printf("»»»»»»»»»»»»»»»»»%d STORED in T1 \n\r",fifo_index);
}
else if (flag2[fifo_hash_index]==0 && fifo_index!=999999999)
{
data2[fifo_hash_index] =fifo_data;
index2[fifo_hash_index] =fifo_index;
flag2[fifo_hash_index]=1;
read_from_fifo=1;
xil_printf("»»»»»»»»»»»»»»»»»%d STORED in T2 \n\r",fifo_index);
}
else if (flag3[fifo_hash_index]==0 && fifo_index!=999999999)
{
data3[fifo_hash_index] =fifo_data;
index3[fifo_hash_index] =fifo_index;
flag3[fifo_hash_index]=1;
read_from_fifo=1;
xil_printf("»»»»»»»»»»»»»»»»»%d STORED in T3 \n\r",fifo_index);
}
else
read_from_fifo=0;
} // Store in memory
else
{
xil_printf("ERROR ! Index %d cannot be found !!!!\n\r",consumer_index);
consumer_done=0;
consumer_index++;
}
}
}
xil_printf ("consumer_index =%d \t ci=%d \n\r",consumer_index,ci);
end = XTmrCtr_GetValue(&timer, TIMER_COUNTER_0);
XTmrCtr_Stop(&timer, TIMER_COUNTER_0);
xil_printf("Timer Start value = %d Timer end value = %d \r\n", start, end-start);
return 0;
}
int main(void) {
u32 cmd;
u32 count;
u32 GenerateValue, CaptureDuration;
u8 NumberOfTimes;
u32 count1, count2;
u32 status;
u8 iop_pins[8];
u32 timer_pin;
// Initialize Pmod
pmod_init(0,1);
/*
* Configuring Pmod IO switch
* Timer is connected to bit[0] of the Channel 1 of AXI GPIO instance
* This configuration is changed later
*/
config_pmod_switch(TIMER, GPIO_1, GPIO_2, GPIO_3,
GPIO_4, GPIO_5, GPIO_6, GPIO_7);
// by default tristate timer output
Xil_Out32(XPAR_GPIO_0_BASEADDR+0x08,1);
while(1){
while(MAILBOX_CMD_ADDR==0); // wait for CMD to be issued
cmd = MAILBOX_CMD_ADDR;
switch(cmd){
case CONFIG_IOP_SWITCH:
// read new pin configuration
timer_pin = MAILBOX_DATA(0);
iop_pins[0] = GPIO_0;
iop_pins[1] = GPIO_1;
iop_pins[2] = GPIO_2;
iop_pins[3] = GPIO_3;
iop_pins[4] = GPIO_4;
iop_pins[5] = GPIO_5;
iop_pins[6] = GPIO_6;
iop_pins[7] = GPIO_7;
// set new pin configuration
iop_pins[timer_pin] = TIMER;
config_pmod_switch(iop_pins[0], iop_pins[1], iop_pins[2],
iop_pins[3], iop_pins[4], iop_pins[5],
iop_pins[6], iop_pins[7]);
Xil_Out32(XPAR_GPIO_0_BASEADDR+0x08,1);
MAILBOX_CMD_ADDR = 0x0;
break;
case STOP_TIMER:
XTmrCtr_Stop(&TimerInst_0, 0);
XTmrCtr_Stop(&TimerInst_0, 1);
MAILBOX_CMD_ADDR = 0x0;
break;
case GENERATE_FOREVER:
// tri-state control negated so output can be driven
Xil_Out32(XPAR_GPIO_0_BASEADDR+0x08,0);
// get period value in multiple of 10 ns clock period
GenerateValue=MAILBOX_DATA(0);
XTmrCtr_SetResetValue(&TimerInst_0, 0, GenerateValue);
XTmrCtr_SetOptions(&TimerInst_0, 0,
XTC_AUTO_RELOAD_OPTION | XTC_CSR_LOAD_MASK |
XTC_CSR_EXT_GENERATE_MASK | XTC_CSR_DOWN_COUNT_MASK);
XTmrCtr_Start(&TimerInst_0, 0);
MAILBOX_CMD_ADDR = 0x0;
break;
case GENERATE_N_TIMES:
// tri-state control negated so output can be driven
Xil_Out32(XPAR_GPIO_0_BASEADDR+0x08,0);
// bits 7:0 number of times, rest is period
GenerateValue=MAILBOX_DATA(0)>>8;
NumberOfTimes=MAILBOX_DATA(0) & 0xff;
XTmrCtr_SetResetValue(&TimerInst_0, 0, GenerateValue);
XTmrCtr_SetOptions(&TimerInst_0, 0,
XTC_AUTO_RELOAD_OPTION | XTC_CSR_LOAD_MASK |
XTC_CSR_EXT_GENERATE_MASK | XTC_CSR_DOWN_COUNT_MASK);
XTmrCtr_Start(&TimerInst_0, 0);
while(NumberOfTimes){
// wait for NumberOfTimes to count down to 0
status=XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0, TCSR0);
if(status & 0x100){
// wait for the asserted edge, reset the flag
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0, status);
NumberOfTimes--;
}
}
XTmrCtr_Stop(&TimerInst_0, 0);
MAILBOX_CMD_ADDR = 0x0;
break;
case EVENT_OCCURED:
// tri-state control asserted to enable input to capture
Xil_Out32(XPAR_GPIO_0_BASEADDR+0x08,1);
// get period value in multiple of 10 ns clock period
CaptureDuration=MAILBOX_DATA(0);
/*
* Use timer module 0 for event counts
* Use timer module 1 for the duration
* Load timer 1's Load register
*/
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1,
TLR0, CaptureDuration);
/*
* 0001 0010 0010 => no cascade, no all timers,
* no pwm, clear interrupt status,
* disable timer, no interrupt,
* load timer, hold capture value,
* disable external capture,
* disable external generate,
* down counter, generate mode
*/
// clear int flag and load counter
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1, TCSR0, 0x122);
// enable timer 1 in compare mode, no load counter
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1, TCSR0, 0x082);
/*
* 0001 1000 1001 => no cascade, no all timers,
* no pwm, clear interrupt status,
* enable timer, no interrupt,
* no load timer, hold capture value,
* enable external capture,
* disable external generate,
* up counter, capture mode
*/
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0, TCSR0, 0x189);
while(1) {
if((XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 1,
TCSR0) & 0x100)){
// if duration over then get out, disable counter 1
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1,
TCSR0, 0x100);
MAILBOX_DATA(0)=0;
break;
}
if((XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0) & 0x100)){
// wait for the asserted edge, disable counter 0
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0, 0x100);
MAILBOX_DATA(0)=1;
break;
}
}
MAILBOX_CMD_ADDR = 0x0;
break;
case COUNT_EVENTS:
// tri-state control asserted to enable input to capture
Xil_Out32(XPAR_GPIO_0_BASEADDR+0x08,1);
// get period value in multiple of 10 ns clock period
CaptureDuration=MAILBOX_DATA(0);
count=0;
/*
* Use timer module 0 for event counts
* Use timer module 1 for the duration
* Load timer 1's Load register
*/
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1,
TLR0, CaptureDuration);
/*
* 0001 0010 0010 => no cascade, no all timers, no pwm,
* clear interrupt status, disable timer,
* no interrupt, load timer,
* hold capture value,
* disable external capture,
* disable external generate,
* down counter, generate mode
*/
// clear int flag and load counter
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1, TCSR0, 0x122);
// enable timer 1 in compare mode, no load counter
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1, TCSR0, 0x082);
/* 0001 1000 1001 => no cascade, no all timers, no pwm,
* clear interrupt status, enable timer,
* no interrupt, no load timer,
* hold capture value,
* enable external capture,
* disable external generate, up counter,
* capture mode
*/
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0, TCSR0, 0x189);
while(1) {
if((XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 1,
TCSR0) & 0x100)){
// if duration over then get out, disable counter 1
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 1,
TCSR0, 0x100);
break;
}
if((XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0) & 0x100)){
// wait for the asserted edge
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0, 0x189);
count++;
}
}
MAILBOX_DATA(0)=count;
MAILBOX_CMD_ADDR = 0x0;
break;
case MEASURE_PERIOD:
// tri-state control asserted to enable input to capture
Xil_Out32(XPAR_GPIO_0_BASEADDR+0x08,1);
/*
* Use timer module 0 for event capture
* Use module 1 for the maximum duration
*/
count1=0;
count2=0;
/*
* 0001 1000 1001 => no cascade, no all timers, no pwm,
* clear interrupt status, enable timer,
* no interrupt, no load timer,
* hold capture value,
* enable external capture,
* disable external generate,
* up counter, capture mode
*/
// clear capture flag and enable capture mode
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0, TCSR0, 0x189);
// skip high or 1st asserted edge
while(!(XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0) & 0x100));
// dummy read
XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0, TLR0);
// clear capture flag and enable capture mode
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0, TCSR0, 0x189);
// wait for 1st asserted edge
while(!(XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0) & 0x100));
// read counter value
count1=XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0, TLR0);
// reset interrupt flag
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0, TCSR0, 0x189);
// wait for 2nd asserted edge
while(!(XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0,
TCSR0) & 0x100));
// read counter value
count2=XTmrCtr_ReadReg(XPAR_TMRCTR_0_BASEADDR, 0, TLR0);
// clear capture flag and disable
XTmrCtr_WriteReg(XPAR_TMRCTR_0_BASEADDR, 0, TCSR0, 0x100);
MAILBOX_DATA(0)=count2-count1;
MAILBOX_CMD_ADDR = 0x0;
break;
default:
MAILBOX_CMD_ADDR = 0x0;
break;
}
}
return 0;
}
void stopTimer(u8 TmrCtrNumber) {
XTmrCtr_Stop(&timer, TmrCtrNumber);
}
