void init_all(void) {
XIntc_Initialize(&intc, XPAR_XPS_INTC_0_DEVICE_ID);
microblaze_enable_interrupts();
XIntc_mMasterEnable(XPAR_INTC_0_BASEADDR);
XUartLite_mEnableIntr(XPAR_UARTLITE_0_BASEADDR);
//// пецхярпюжхъ напюанрвхйнб ////////////////////////////////////////////
XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
XPAR_INTC_0_UARTLITE_0_VEC_ID,
(XInterruptHandler)handler_RS232,
(void *)0);
XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
XPAR_INTC_0_TMRCTR_0_VEC_ID,
(XInterruptHandler)handler_Timer,
(void *)0);
///////////////////////////////////////////////////////////////////////////////
//// мюярпнийю рюилепю //////////////////////////////////////////////////////
XTmrCtr_mSetLoadReg(XPAR_XPS_TIMER_0_BASEADDR,
0,
0x61a8 //(25 MHz / 25000 = 1mS
//0x124F8//(75 MHz : 75.000 = 1 mS
);
XIntc_mEnableIntr(XPAR_INTC_0_BASEADDR,
// XPAR_XPS_TIMER_0_INTERRUPT_MASK |
XPAR_XPS_UARTLITE_0_INTERRUPT_MASK);
XTmrCtr_mSetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR,
0,
XTC_CSR_ENABLE_TMR_MASK |
XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK |
XTC_CSR_DOWN_COUNT_MASK);
/////////////////////////////////////////////////////////////////////////////////
///////// мюярпнийю сярпниярб ббндю-бшбндю ////////////////////////////////////
XGpio_Initialize(&photo, XPAR_XPS_GPIO_0_DEVICE_ID);
XGpio_Initialize(&ircom, XPAR_XPS_GPIO_1_DEVICE_ID);
XGpio_Initialize(&kt, XPAR_XPS_GPIO_2_DEVICE_ID);
XGpio_SetDataDirection(&photo, 1, 0xffffffff); // ББНД
XGpio_SetDataDirection(&photo, 2, 0x00); // БШБНД
XGpio_SetDataDirection(&ircom, 1, 0x00); // БШБНД
XGpio_SetDataDirection(&ircom, 2, 0x00); // БШБНД
XGpio_SetDataDirection(&kt, 1, 0x00); // БШБНД
};
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulControlReg, ulMask;
/* NOTE: The baud rate used by this driver is determined by the hardware
parameterization of the UART Lite peripheral, and the baud value passed to
this function has no effect. */
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
if( ( xRxedChars ) && ( xCharsForTx ) )
{
/* Disable the interrupt. */
XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
/* Flush the fifos. */
ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
/* Enable the interrupt again. The interrupt controller has not yet been
initialised so there is no chance of receiving an interrupt until the
scheduler has been started. */
XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
/* Enable the interrupt in the interrupt controller while maintaining
all the other bit settings. */
ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
}
return ( xComPortHandle ) 0;
}
