/**
*
* Set up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to set up the
* configuration for.
*
* @return A pointer to the device configuration for the specified
* device ID. See xipipsu.h for the definition of
* XIpiPsu_Config.
*
* @note This is for safety use case where in this function has to
* be called before CfgInitialize. So that driver will be
* initialized with the provided configuration. For non-safe
* use cases, this is not needed.
*
******************************************************************************/
void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr)
{
u32 Index;
Xil_AssertVoid(ConfigTblPtr != NULL);
for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
XIpiPsu_ConfigTable[Index].BaseAddress = ConfigTblPtr->BaseAddress;
XIpiPsu_ConfigTable[Index].BitMask = ConfigTblPtr->BitMask;
XIpiPsu_ConfigTable[Index].BufferIndex = ConfigTblPtr->BufferIndex;
XIpiPsu_ConfigTable[Index].IntId = ConfigTblPtr->IntId;
}
}
}
/**
*
* Acknowledges the interrupt source provided as the argument Id. When the
* interrupt is acknowledged, it causes the interrupt controller to clear its
* interrupt condition.
*
* @param InstancePtr is a pointer to the XIOModule instance to be
* worked on.
* @param Id contains the ID of the interrupt source and should be in
* the range of 0 to XPAR_IOMODULE_INTC_MAX_INTR_SIZE - 1
* with 0 being the highest priority interrupt.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XIOModule_Acknowledge(XIOModule * InstancePtr, u8 Id)
{
u32 Mask;
/*
* Assert the arguments
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Id < XPAR_IOMODULE_INTC_MAX_INTR_SIZE);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* The Id is used to create the appropriate mask for the
* desired bit position. Id currently limited to 0 - 31
*/
Mask = XIOModule_BitPosMask[Id];
/*
* Acknowledge the selected interrupt source, no read of the acknowledge
* register is necessary since only the bits set in the mask will be
* affected by the write
*/
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Mask);
}
/**
*
* This function is the interrupt handler for the Dual Splitter core.
*
* This handler reads the pending interrupt from the GENR_ERROR register,
* determines the source of the interrupts and calls the respective
* callbacks for the interrupts that are enabled in IRQ_ENABLE register,
* and finally clears the interrupts.
*
* The application is responsible for connecting this function to the interrupt
* system. Application beyond this core is also responsible for providing
* callbacks to handle interrupts and installing the callbacks using
* XDualSplitter_SetCallBack() during initialization phase.
*
* @param InstancePtr is a pointer to the XDualSplitter core instance.
*
* @return None.
*
* @note Interrupt should be enabled to execute interrupt handler.
*
******************************************************************************/
void XDualSplitter_IntrHandler(void *InstancePtr)
{
u32 PendingIntr;
u32 ErrorStatus;
XDualSplitter *XDualSpltrPtr = (XDualSplitter *)((void *)InstancePtr);
/* Verify arguments. */
Xil_AssertVoid(XDualSpltrPtr != NULL);
Xil_AssertVoid(XDualSpltrPtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(XDualSpltrPtr->Config.HasIntrReq == 0x1);
/* Get pending interrupts */
PendingIntr = XDualSplitter_IntrGetPending(XDualSpltrPtr);
/* Interrupt has happened due to error(s) */
if (PendingIntr & XDUSP_ALL_ERR_MASK) {
ErrorStatus = PendingIntr & (u32)XDUSP_ALL_ERR_MASK;
XDualSpltrPtr->ErrCallback(XDualSpltrPtr->ErrRef, ErrorStatus);
}
/* Clear pending interrupt(s) */
XDualSplitter_IntrClear(XDualSpltrPtr, PendingIntr);
}
/**
* Gets the interrupt priority and trigger type for the specificd IRQ source.
*
* @param BaseAddr is the device base address
* @param Int_Id is the IRQ source number to modify
* @param Priority is a pointer to the value of the priority of the IRQ
* source. This is a return value.
* @param Trigger is pointer to the value of the trigger of the IRQ
* source. This is a return value.
*
* @return None.
*
* @note This API has the similar functionality of XScuGic_GetPriority
* TriggerType() and should be used when there is no InstancePtr.
*
*****************************************************************************/
void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
u8 *Priority, u8 *Trigger)
{
u32 RegValue;
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
Xil_AssertVoid(Priority != NULL);
Xil_AssertVoid(Trigger != NULL);
/*
* Determine the register to read to using the Int_Id.
*/
RegValue = XScuGic_ReadReg(DistBaseAddress,
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
/*
* Shift and Mask the correct bits for the priority and trigger in the
* register
*/
RegValue = RegValue >> ((Int_Id%4U)*8U);
*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
/*
* Determine the register to read to using the Int_Id.
*/
RegValue = XScuGic_ReadReg(DistBaseAddress,
XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
/*
* Shift and Mask the correct bits for the priority and trigger in the
* register
*/
RegValue = RegValue >> ((Int_Id%16U)*2U);
*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
}
/**
*
* Write data to the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number to which the Data is to be written.
* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
* @param Data is the data to be written to the specified pin (0 or 1).
*
* @return None.
*
* @note This function does a masked write to the specified pin of
* the specified GPIO bank. The previous state of other pins
* is maintained.
*
*****************************************************************************/
void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data)
{
u32 RegOffset;
u32 Value;
u8 Bank;
u8 PinNumber;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
/*
* Get the Bank number and Pin number within the bank.
*/
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
if (PinNumber > 15) {
/*
* There are only 16 data bits in bit maskable register.
*/
PinNumber -= 16;
RegOffset = XGPIOPS_DATA_MSW_OFFSET;
} else {
RegOffset = XGPIOPS_DATA_LSW_OFFSET;
}
/*
* Get the 32 bit value to be written to the Mask/Data register where
* the upper 16 bits is the mask and lower 16 bits is the data.
*/
Data &= 0x01;
Value = ~(1 << (PinNumber + 16)) & ((Data << PinNumber) | 0xFFFF0000);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_DATA_MASK_OFFSET) +
RegOffset, Value);
}
/**
*
* Disables the interrupt source provided as the argument Int_Id such that the
* interrupt controller will not cause interrupts for the specified Int_Id. The
* interrupt controller will continue to hold an interrupt condition for the
* Int_Id, but will not cause an interrupt.
*
* @param InstancePtr is a pointer to the XScuGic instance.
* @param Int_Id contains the ID of the interrupt source and should be
* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
{
u32 Mask;
/*
* Assert the arguments
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* The Int_Id is used to create the appropriate mask for the
* desired bit position. Int_Id currently limited to 0 - 31
*/
Mask = 0x00000001 << (Int_Id % 32);
/*
* Disable the selected interrupt source by setting the
* corresponding bit in the IDR.
*/
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DISABLE_OFFSET +
((Int_Id / 32) * 4), Mask);
}
/**
*
* Stops the timer counter by disabling it.
*
* It is the callers' responsibility to disconnect the interrupt handler of the
* timer_counter from the interrupt source, typically an interrupt controller,
* and disable the interrupt within the interrupt controller.
*
* @param InstancePtr is a pointer to the XTmrCtr instance.
* @param TmrCtrNumber is the timer counter of the device to operate on.
* Each device may contain multiple timer counters. The timer
* number is a zero based number with a range of
* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
{
u32 ControlStatusReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read the current register contents
*/
ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
TmrCtrNumber, XTC_TCSR_OFFSET);
/*
* Disable the timer counter such that it's not running
*/
ControlStatusReg &= ~(XTC_CSR_ENABLE_TMR_MASK);
/*
* Write out the updated value to the actual register.
*/
XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
XTC_TCSR_OFFSET, ControlStatusReg);
}
/**
*
* Starts the specified timer counter of the device such that it starts running.
* The timer counter is reset before it is started and the reset value is
* loaded into the timer counter.
*
* If interrupt mode is specified in the options, it is necessary for the caller
* to connect the interrupt handler of the timer to the interrupt source,
* typically an interrupt controller, and enable the interrupt within the
* interrupt controller.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param TimerNumber is the timer of the device to operate on.
* Each device may contain multiple timers. The timer
* number is a zero based number with a range of
* 0 to (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIOModule_Timer_Start(XIOModule * InstancePtr, u8 TimerNumber)
{
u32 NewControlStatus;
u32 TimerOffset = TimerNumber << XTC_TIMER_COUNTER_SHIFT;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(TimerNumber < XTC_DEVICE_TIMER_COUNT);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Set the new value the current contents such that only the necessary
* bits of the register are modified in the following operations
*/
NewControlStatus = InstancePtr->CurrentTCSR[TimerNumber] |
XTC_CSR_ENABLE_TMR_MASK;
/*
* Remove the reset condition such that the timer starts
* running with the value loaded from the compare register
*/
XIOModule_WriteReg(InstancePtr->BaseAddress,
TimerOffset + XTC_TCSR_OFFSET, NewControlStatus);
InstancePtr->CurrentTCSR[TimerNumber] = NewControlStatus;
}
/**
* This handles an interrupt generated by a HDCP port device.
*
* @param InstancePtr is the device to write to.
* @param IntCause is the interrupt cause bit map.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XHdcp1x_PortHandleInterrupt(XHdcp1x *InstancePtr, u32 IntCause)
{
const XHdcp1x_PortPhyIfAdaptor *Adaptor = NULL;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Determine Adaptor */
Adaptor = InstancePtr->Port.Adaptor;
/* Check for adaptor function and invoke if present */
if ((Adaptor != NULL) && (Adaptor->IntrHandler != NULL)) {
InstancePtr->Port.Stats.IntCount++;
(*(Adaptor->IntrHandler))(InstancePtr, IntCause);
}
}
/**
*
* This function prints LBox IP status on the console
*
* @param InstancePtr is the pointer to the core instance.
*
* @return None
*
******************************************************************************/
void XV_LBoxDbgReportStatus(XV_letterbox *InstancePtr)
{
XV_letterbox *pLbox = InstancePtr;
u32 done, idle, ready, ctrl;
u32 colstart, colend, rowstart, rowend;
u32 yr,cbg,crb, cfmt, width, height;
/*
* Assert validates the input arguments
*/
Xil_AssertVoid(InstancePtr != NULL);
xil_printf("\r\n\r\n----->LBOX IP STATUS<----\r\n");
done = XV_letterbox_IsDone(pLbox);
idle = XV_letterbox_IsIdle(pLbox);
ready = XV_letterbox_IsReady(pLbox);
ctrl = XV_letterbox_ReadReg(pLbox->Config.BaseAddress, XV_LETTERBOX_CTRL_ADDR_AP_CTRL);
colstart = XV_letterbox_Get_HwReg_col_start(pLbox);
colend = XV_letterbox_Get_HwReg_col_end(pLbox);
rowstart = XV_letterbox_Get_HwReg_row_start(pLbox);
rowend = XV_letterbox_Get_HwReg_row_end(pLbox);
yr = XV_letterbox_Get_HwReg_Y_R_value(pLbox);
cbg = XV_letterbox_Get_HwReg_Cb_G_value(pLbox);
crb = XV_letterbox_Get_HwReg_Cr_B_value(pLbox);
height = XV_letterbox_Get_HwReg_height(pLbox);
width = XV_letterbox_Get_HwReg_width(pLbox);
cfmt = XV_letterbox_Get_HwReg_video_format(pLbox);
xil_printf("IsDone: %d\r\n", done);
xil_printf("IsIdle: %d\r\n", idle);
xil_printf("IsReady: %d\r\n", ready);
xil_printf("Ctrl: 0x%x\r\n\r\n", ctrl);
xil_printf(" Window Start X : %d\r\n",colstart);
xil_printf(" Window End X : %d\r\n",colend);
xil_printf(" Window Start Y : %d\r\n",rowstart);
xil_printf(" Window End Y : %d\r\n",rowend);
xil_printf(" Frame Width : %d\r\n",width);
xil_printf(" Frame Height : %d\r\n",height);
xil_printf(" Color Format : %d\r\n",cfmt);
xil_printf(" Bkgnd Color Y/R: %d\r\n",yr);
xil_printf(" Bkgnd Color U/G: %d\r\n",cbg);
xil_printf(" Bkgnd Color V/B: %d\r\n",crb);
}
/**
* This funtion is registered to handle callbacks for endpoint 0 (Control).
*
* It is called from an interrupt context such that the amount of processing
* performed should be minimized.
*
*
* @param CallBackRef is the reference passed in when the function
* was registered.
* @param EpNum is the Number of the endpoint on which the event occured.
* @param EventType is type of the event that occured.
*
* @return None.
*
******************************************************************************/
static void XUsbPs_Ep0EventHandler(void *CallBackRef, u8 EpNum,
u8 EventType, void *Data)
{
XUsbPs *InstancePtr;
int Status;
XUsbPs_SetupData SetupData;
u8 *BufferPtr;
u32 BufferLen;
u32 Handle;
Xil_AssertVoid(NULL != CallBackRef);
InstancePtr = (XUsbPs *) CallBackRef;
switch (EventType) {
/* Handle the Setup Packets received on Endpoint 0. */
case XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED:
Status = XUsbPs_EpGetSetupData(InstancePtr, EpNum, &SetupData);
if (XST_SUCCESS == Status) {
/* Handle the setup packet. */
(int) XUsbPs_Ch9HandleSetupPacket(InstancePtr,
&SetupData);
}
break;
/* We get data RX events for 0 length packets on endpoint 0. We receive
* and immediately release them again here, but there's no action to be
* taken.
*/
case XUSBPS_EP_EVENT_DATA_RX:
/* Get the data buffer. */
Status = XUsbPs_EpBufferReceive(InstancePtr, EpNum,
&BufferPtr, &BufferLen, &Handle);
if (XST_SUCCESS == Status) {
/* Return the buffer. */
XUsbPs_EpBufferRelease(Handle);
}
break;
default:
/* Unhandled event. Ignore. */
break;
}
}
/**
*
* This function sets the interrupt mask.
*
* @param InstancePtr is a pointer to the XUartPs instance
* @param Mask contains the interrupts to be enabled or disabled.
* A '1' enables an interupt, and a '0' disables.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
{
u32 TempMask = Mask;
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
TempMask &= (u32)XUARTPS_IXR_MASK;
/* Write the mask to the IER Register */
XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_IER_OFFSET, TempMask);
/* Write the inverse of the Mask to the IDR register */
XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
XUARTPS_IDR_OFFSET, (~TempMask));
}
/**
* This function configures the letterbox active window. All pixels within the
* window are passed to the output as-is. Any pixel outside the defined window
* will be clamped to the programmed background color
*
* @param InstancePtr is a pointer to the core instance to be worked on.
* @param ActiveWindow is structure that contains window coordinates and size
* @param FrameWidth is the input stream width
* @param FrameHeight is the input stream height
*
* @return None
*
******************************************************************************/
void XV_LBoxSetActiveWin(XV_Lbox_l2 *InstancePtr,
XVidC_VideoWindow *ActiveWindow,
u32 FrameWidth,
u32 FrameHeight)
{
Xil_AssertVoid(InstancePtr != NULL);
XV_letterbox_Set_HwReg_col_start(&InstancePtr->Lbox, ActiveWindow->StartX);
XV_letterbox_Set_HwReg_col_end(&InstancePtr->Lbox,
(ActiveWindow->StartX+ActiveWindow->Width-1));
XV_letterbox_Set_HwReg_row_start(&InstancePtr->Lbox, ActiveWindow->StartY);
XV_letterbox_Set_HwReg_row_end(&InstancePtr->Lbox,
(ActiveWindow->StartY+ActiveWindow->Height-1));
XV_letterbox_Set_HwReg_height(&InstancePtr->Lbox, FrameHeight);
XV_letterbox_Set_HwReg_width(&InstancePtr->Lbox, FrameWidth);
}
/**
* This function process a read of the Binfo register by the tx device.
*
* @param CallbackRef is the device to whose register was read.
*
* @return None.
*
* @note This function initiates the side effects of the tx device read
* the Binfo register. This is currently limited to the clearing of
* bits within device's Bstatus register.
*
******************************************************************************/
static void XHdcp1x_PortDpRxProcessBinfoRead(void *CallbackRef)
{
XHdcp1x *InstancePtr = CallbackRef;
u8 Value = 0;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Update statistics */
InstancePtr->Port.Stats.IntCount++;
/* Clear bit 0 of Bstatus register */
XHdcp1x_PortDpRxRead(InstancePtr, XHDCP1X_PORT_OFFSET_BSTATUS,
&Value, 1);
Value &= 0xFEu;
XHdcp1x_PortDpRxWrite(InstancePtr, XHDCP1X_PORT_OFFSET_BSTATUS,
&Value, 1);
}
/**
*
* This function sets the input/output frame size in Active Size register and
* enables the register update.
*
* @param InstancePtr is a pointer to the Xccm instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XCcm_Setup(XCcm *InstancePtr)
{
u32 Data;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
XCcm_RegUpdateDisable(InstancePtr);
/* Write into active size register */
Data = ((((InstancePtr->VSize)) <<
(u32)(XCCM_ACTSIZE_NUM_LINE_SHIFT)) &
(XCCM_ACTSIZE_NUM_LINE_MASK)) |
(((InstancePtr->HSize)) & (u32)(XCCM_ACTSIZE_NUM_PIXEL_MASK));
XCcm_WriteReg(InstancePtr->Config.BaseAddress,
(XCCM_ACTIVE_SIZE_OFFSET), Data);
XCcm_RegUpdateEnable(InstancePtr);
}
/**
*
* Write all the RSA data used for decryption (Modulus, Exponent etc.) at
* corresponding offsets in RSA RAM.
*
* @param InstancePtr is a pointer to the XSecure_Rsa instance.
*
* @return None.
*
* @note None
*
******************************************************************************/
static void XSecure_RsaPutData(XSecure_Rsa *InstancePtr)
{
/* Assert validates the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
/* Initialize Modular exponentiation */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->ModExpo,
XSECURE_CSU_RSA_RAM_EXPO);
/* Initialize Modular. */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->Mod,
XSECURE_CSU_RSA_RAM_MOD);
/* Initialize Modular extension (R*R Mod M) */
XSecure_RsaWriteMem(InstancePtr, (u32 *)InstancePtr->ModExt,
XSECURE_CSU_RSA_RAM_RES_Y);
}
/**
*
* This function clears all vertical coefficients of a the Chroma Resampler
* which are previously set.
*
* @param InstancePtr is a pointer to the XCresample instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XCresample_Clear_VCoef_Values (XCresample *InstancePtr)
{
u32 Index1;
u32 Index2;
u32 Offset;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Offset = XCRE_COEF00_VPHASE0_OFFSET;
/* Set all vertical coefficient values to 0 */
for (Index1 = 0; Index1 < XCRE_NUM_OF_PHASES; Index1++) {
for (Index2 = 0; Index2 < XCRE_NUM_VCOEFS; Index2++) {
XCresample_WriteReg(InstancePtr->Config.BaseAddress,
Offset, 0x00);
Offset = Offset + XCRE_OFFSET_DIFF;
}
}
}
/**
* Processes an Event entry in Event Buffer.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Event is the Event entry.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XUsbPsu_ProcessEvent(struct XUsbPsu *InstancePtr,
const union XUsbPsu_Event *Event)
{
Xil_AssertVoid(Event != NULL);
if (Event->Type.Is_DevEvt == 0) {
/* Device Endpoint Event */
return XUsbPsu_EpInterrupt(InstancePtr, &Event->Epevt);
}
switch (Event->Type.Type) {
case XUSBPSU_EVENT_TYPE_DEV:
XUsbPsu_DevInterrupt(InstancePtr, &Event->Devt);
break;
/* Carkit and I2C events not supported now */
default:
break;
}
}
/**
*
* This function is the interrupt handler for the ZDMA core.
*
* This handler reads the pending interrupt from Status register, determines the
* source of the interrupts and calls the respective callbacks for the
* interrupts that are enabled in IRQ_ENABLE register, and finally clears the
* interrupts.
*
* The application is responsible for connecting this function to the interrupt
* system. Application beyond this driver is also responsible for providing
* callbacks to handle interrupts and installing the callbacks using
* XZDma_SetCallBack() during initialization phase. .
*
* @param Instance is a pointer to the XZDma instance to be worked on.
*
* @return None.
*
* @note To generate interrupt required interrupts should be enabled.
*
******************************************************************************/
void XZDma_IntrHandler(void *Instance)
{
u32 PendingIntr;
u32 ErrorStatus;
XZDma *InstancePtr = NULL;
InstancePtr = (XZDma *)((void *)Instance);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Get pending interrupts */
PendingIntr = (u32)(XZDma_IntrGetStatus(InstancePtr));
PendingIntr &= (~XZDma_GetIntrMask(InstancePtr));
/* ZDMA transfer has completed */
ErrorStatus = (PendingIntr) & (XZDMA_IXR_DMA_DONE_MASK);
if ((ErrorStatus) != 0U) {
XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
InstancePtr->ChannelState = XZDMA_IDLE;
InstancePtr->DoneHandler(InstancePtr->DoneRef);
}
/* An error has been occurred */
ErrorStatus = PendingIntr & (XZDMA_IXR_ERR_MASK);
if ((ErrorStatus) != 0U) {
if ((ErrorStatus & XZDMA_IXR_DMA_PAUSE_MASK) ==
XZDMA_IXR_DMA_PAUSE_MASK) {
InstancePtr->ChannelState = XZDMA_PAUSE;
}
else {
if ((ErrorStatus & (XZDMA_IXR_AXI_WR_DATA_MASK |
XZDMA_IXR_AXI_RD_DATA_MASK |
XZDMA_IXR_AXI_RD_DST_DSCR_MASK |
XZDMA_IXR_AXI_RD_SRC_DSCR_MASK)) != 0x00U) {
InstancePtr->ChannelState = XZDMA_IDLE;
}
}
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, ErrorStatus);
}
/* Clear pending interrupt(s) */
XZDma_IntrClear(InstancePtr, PendingIntr);
}
/**
* This funtion is registered to handle callbacks for endpoint 1 (Bulk data).
*
* It is called from an interrupt context such that the amount of processing
* performed should be minimized.
*
*
* @param CallBackRef is the reference passed in when the function was
* registered.
* @param EpNum is the Number of the endpoint on which the event occured.
* @param EventType is type of the event that occured.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void XUsbPs_Ep1EventHandler(void *CallBackRef, u8 EpNum,
u8 EventType, void *Data)
{
XUsbPs *InstancePtr;
int Status;
u8 *BufferPtr;
u32 BufferLen;
u32 InavalidateLen;
u32 Handle;
Xil_AssertVoid(NULL != CallBackRef);
InstancePtr = (XUsbPs *) CallBackRef;
switch (EventType) {
case XUSBPS_EP_EVENT_DATA_RX:
/* Get the data buffer.*/
Status = XUsbPs_EpBufferReceive(InstancePtr, EpNum,
&BufferPtr, &BufferLen, &Handle);
/* Invalidate the Buffer Pointer */
InavalidateLen = BufferLen;
if (BufferLen % 32) {
InavalidateLen = (BufferLen/32) * 32 + 32;
}
Xil_DCacheInvalidateRange((unsigned int)BufferPtr,
InavalidateLen);
if (XST_SUCCESS == Status) {
/* Handle the storage class request. */
XUsbPs_HandleStorageReq(InstancePtr, EpNum,
BufferPtr, BufferLen);
/* Release the buffer. */
XUsbPs_EpBufferRelease(Handle);
}
break;
default:
/* Unhandled event. Ignore. */
break;
}
}
/**
*
* This function sets up double buffered active size register and enables the
* register update.
*
* @param InstancePtr is a pointer to the XYCrCb2Rgb instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XYCrCb2Rgb_Setup(XYCrCb2Rgb *InstancePtr)
{
u32 ActiveSize;
/* Verify argument. */
Xil_AssertVoid(InstancePtr != NULL);
XYCrCb2Rgb_RegUpdateDisable(InstancePtr);
/* Write into active size register */
ActiveSize = ((((u32)InstancePtr->VSize) &
(u32)(XYCC_ACTSIZE_NUM_PIXEL_MASK)) <<
(XYCC_ACTSIZE_NUM_LINE_SHIFT)) |
((InstancePtr->HSize) &
(u32)(XYCC_ACTSIZE_NUM_PIXEL_MASK));
XYCrCb2Rgb_WriteReg(InstancePtr->Config.BaseAddress,
(XYCC_ACTIVE_SIZE_OFFSET), ActiveSize);
XYCrCb2Rgb_RegUpdateEnable(InstancePtr);
}
/**
* This handles an interrupt generated by a HDCP port device.
*
* @param InstancePtr is the device to write to.
* @param IntCause is the interrupt cause bit map.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void XHdcp1x_PortDpTxIntrHandler(XHdcp1x *InstancePtr, u32 IntCause)
{
int HpdDetected = 0;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Determine HpdDetected */
if (IntCause & XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK) {
HpdDetected = TRUE;
}
else if (IntCause & XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK) {
HpdDetected = TRUE;
}
/* Check for HPD irq */
if (HpdDetected) {
XHdcp1x_CheckForRxStatusChange(InstancePtr);
}
}
/**
* This function initializes all the data structures of the XAVBuf Instance.
*
* @param InstancePtr is a pointer to the XAVBuf instance.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void XAVBuf_Initialize(XAVBuf *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
InstancePtr->AVMode.NonLiveVideo = NULL;
InstancePtr->AVMode.LiveVideo = NULL;
InstancePtr->AVMode.LiveGraphics = NULL;
InstancePtr->AVMode.NonLiveGraphics = NULL;
InstancePtr->AVMode.VideoSrc = XAVBUF_VIDSTREAM1_NONE;
InstancePtr->AVMode.GraphicsSrc = XAVBUF_VIDSTREAM2_NONE;
InstancePtr->AVMode.Audio = NULL;
InstancePtr->AVMode.GraphicsAudio = NULL;
InstancePtr->AVMode.AudioSrc1 = XAVBUF_AUDSTREAM1_NO_AUDIO;
InstancePtr->AVMode.AudioSrc2 = XAVBUF_AUDSTREAM2_NO_AUDIO;
InstancePtr->Blender.GlobalAlphaEn = 0;
InstancePtr->Blender.Alpha = 0;
InstancePtr->Blender.OutputVideo = NULL;
XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, 0);
}
/**
*
* This function is the interrupt handler for the UART.
* It must be connected to an interrupt system by the user such that it is
* called when an interrupt for any UART lite occurs. This function
* does not save or restore the processor context such that the user must
* ensure this occurs.
*
* @param InstancePtr contains a pointer to the instance of the IOModule
* that the interrupt is for.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIOModule_Uart_InterruptHandler(XIOModule *InstancePtr)
{
u32 IsrStatus;
Xil_AssertVoid(InstancePtr != NULL);
/*
* Read the status register to determine which, could be both,
* interrupt is active
*/
IsrStatus = XIOModule_GetStatusReg(InstancePtr->BaseAddress);
if ((IsrStatus & XUL_SR_RX_FIFO_VALID_DATA) != 0) {
ReceiveDataHandler(InstancePtr);
}
if (((IsrStatus & XUL_SR_TX_FIFO_FULL) == XUL_SR_TX_FIFO_FULL) &&
(InstancePtr->SendBuffer.RequestedBytes > 0)) {
SendDataHandler(InstancePtr);
}
}
/**
* This function returns a previously received data buffer to the driver.
*
* @param Handle is a pointer to the buffer that is returned.
*
* @return None.
*
******************************************************************************/
void XUsbPs_EpBufferRelease(u32 Handle)
{
XUsbPs_dTD *dTDPtr;
/* Perform sanity check on Handle.*/
Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
/* Activate the descriptor and clear the Terminate bit. Make sure to do
* the proper cache handling.
*/
dTDPtr = (XUsbPs_dTD *) Handle;
XUsbPs_dTDInvalidateCache(dTDPtr);
XUsbPs_dTDClrTerminate(dTDPtr);
XUsbPs_dTDSetActive(dTDPtr);
XUsbPs_dTDSetIOC(dTDPtr);
XUsbPs_dTDFlushCache(dTDPtr);
}
/**
* This function enables the slave monitor mode.
*
* It enables slave monitor in the control register and enables
* slave ready interrupt. It then does an address transfer to slave.
* Interrupt handler will signal the caller if slave responds to
* the address transfer.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param SlaveAddr is the address of the slave we want to contact.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
{
u32 BaseAddr;
u32 ConfigReg;
Xil_AssertVoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
/* Clear transfer size register */
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
/*
* Enable slave monitor mode in control register.
*/
ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
/*
* Set up interrupt flag for slave monitor interrupt.
* Dont enable NACK.
*/
XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
/*
* Initialize the slave monitor register.
*/
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
/*
* Set the slave address to start the slave address transmission.
*/
XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
return;
}
/**
*
* This function sets up the RX DMA operation.
*
* @param InstancePtr is a pointer to the XQspiPsu instance.
* @param Msg is a pointer to the structure containing transfer data.
*
* @return None
*
* @note None.
*
******************************************************************************/
static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
XQspiPsu_Msg *Msg)
{
s32 Remainder;
s32 DmaRxBytes;
u64 AddrTemp;
Xil_AssertVoid(InstancePtr != NULL);
AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) &
XQSPIPSU_QSPIDMA_DST_ADDR_MASK);
/* Check for RXBfrPtr to be word aligned */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET,
(u32)AddrTemp);
AddrTemp = AddrTemp >> 32;
if ((AddrTemp & 0xFFFU) != FALSE) {
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
(u32)AddrTemp &
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
}
Remainder = InstancePtr->RxBytes % 4;
DmaRxBytes = InstancePtr->RxBytes;
if (Remainder != 0) {
/* This is done to make Dma bytes aligned */
DmaRxBytes = InstancePtr->RxBytes - Remainder;
Msg->ByteCount = (u32)DmaRxBytes;
}
Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount);
/* Write no. of words to DMA DST SIZE */
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
}
/**
* This function disables slave monitor mode.
*
* @param InstancePtr is a pointer to the XIicPs instance.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
{
u32 BaseAddr;
Xil_AssertVoid(InstancePtr != NULL);
BaseAddr = InstancePtr->Config.BaseAddress;
/*
* Clear slave monitor control bit.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
& (~XIICPS_CR_SLVMON_MASK));
/*
* Clear interrupt flag for slave monitor interrupt.
*/
XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
return;
}
/**
* This function configures the background color to be painted outside active
* window
*
* @param InstancePtr is a pointer to the core instance to be worked on.
* @param ColorId is the background color requested
* @param cfmt is the color format of the input stream
* @param bpc is the color depth (bits per channel)
*
* @return None
*
******************************************************************************/
void XV_LboxSetBackgroundColor(XV_letterbox *InstancePtr,
XLboxColorId ColorId,
XVidC_ColorFormat cfmt,
XVidC_ColorDepth bpc)
{
u16 Cr_b_val,y_r_val,Cb_g_val;
u16 scale;
/*
* Assert validates the input arguments
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((bpc >= XVIDC_BPC_8) &&
(bpc <= InstancePtr->Config.MaxDataWidth))
if(cfmt == XVIDC_CSF_RGB)
{
scale = ((1<<bpc)-1);
y_r_val = bkgndColorRGB[ColorId][0] * scale;
Cb_g_val = bkgndColorRGB[ColorId][1] * scale;
Cr_b_val = bkgndColorRGB[ColorId][2] * scale;
}
else //YUV
{
scale = (1<<(bpc-XVIDC_BPC_8));
y_r_val = bkgndColorYUV[ColorId][0] * scale;
Cb_g_val = bkgndColorYUV[ColorId][1] * scale;
Cr_b_val = bkgndColorYUV[ColorId][2] * scale;
}
/* Set video format */
XV_letterbox_Set_HwReg_video_format(InstancePtr, cfmt);
/* Set Background color (outside window) */
XV_letterbox_Set_HwReg_Y_R_value(InstancePtr, y_r_val);
XV_letterbox_Set_HwReg_Cb_G_value(InstancePtr, Cb_g_val);
XV_letterbox_Set_HwReg_Cr_B_value(InstancePtr, Cr_b_val);
}
/**
*
* Configure SSS and start the SHA-3 engine
*
* @param InstancePtr is a pointer to the XSecure_Sha3 instance.
*
* @return None
*
* @note None
*
******************************************************************************/
void XSecure_Sha3Start(XSecure_Sha3 *InstancePtr)
{
/* Asserts validate the input arguments */
Xil_AssertVoid(InstancePtr != NULL);
InstancePtr->Sha3Len = 0U;
/* Reset SHA3 engine. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_RESET_OFFSET,
XSECURE_CSU_SHA3_RESET_RESET);
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_RESET_OFFSET, 0U);
/* Configure the SSS for SHA3 hashing. */
XSecure_SssSetup(XSecure_SssInputSha3(XSECURE_CSU_SSS_SRC_SRC_DMA));
/* Start SHA3 engine. */
XSecure_WriteReg(InstancePtr->BaseAddress,
XSECURE_CSU_SHA3_START_OFFSET,
XSECURE_CSU_SHA3_START_START);
}
