//------------------------------------------------------------------------------ void main_loop() { #ifdef WRITEBACK Xil_L1DCacheFlush(); #endif uart_loader(); #ifdef WRITEBACK Xil_L1DCacheFlush(); #endif pycoram_main(); }
/** * Modified DCacheFlush to prevent L2 Cache controller access */ void MyXil_DCacheFlush(void) { Xil_L1DCacheFlush(); //Xil_L2CacheFlush(); }