static int nordicsemi_nrf52_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); SystemInit(); #ifdef CONFIG_NRF_ENABLE_ICACHE /* Enable the instruction cache */ NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk; #endif #if defined(CONFIG_SOC_DCDC_NRF52X) nrf_power_dcdcen_set(true); #endif _ClearFaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
/** * @brief Perform basic hardware initialization * * Initialize the interrupt controller device drivers. * Also initialize the timer device driver, if required. * * @return 0 */ static int silabs_efm32wg_init(struct device *arg) { ARG_UNUSED(arg); int oldLevel; /* old interrupt lock level */ /* disable interrupts */ oldLevel = irq_lock(); /* handle chip errata */ CHIP_Init(); _ClearFaults(); /* Initialize system clock according to CONFIG_CMU settings */ clkInit(); /* * install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); /* restore interrupt state */ irq_unlock(oldLevel); return 0; }
static int fsl_frdm_k64f_init(struct device *arg) { ARG_UNUSED(arg); int oldLevel; /* old interrupt lock level */ #if !defined(CONFIG_HAS_SYSMPU) u32_t temp_reg; #endif /* !CONFIG_HAS_SYSMPU */ /* disable interrupts */ oldLevel = irq_lock(); /* release I/O power hold to allow normal run state */ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; #if !defined(CONFIG_HAS_SYSMPU) /* * Disable memory protection and clear slave port errors. * Note that the K64F does not implement the optional ARMv7-M memory * protection unit (MPU), specified by the architecture (PMSAv7), in the * Cortex-M4 core. Instead, the processor includes its own MPU module. */ temp_reg = SYSMPU->CESR; temp_reg &= ~SYSMPU_CESR_VLD_MASK; temp_reg |= SYSMPU_CESR_SPERR_MASK; SYSMPU->CESR = temp_reg; #endif /* !CONFIG_HAS_SYSMPU */ _ClearFaults(); /* Initialize PLL/system clock to 120 MHz */ clkInit(); /* * install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); /* restore interrupt state */ irq_unlock(oldLevel); return 0; }
/** * @brief Perform basic hardware initialization at boot. * * This needs to be run from the very beginning. * So the init priority has to be 0 (zero). * * @return 0 */ static int atmel_sam3x_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); /* Note: * Magic numbers below are obtained by reading the registers * when the SoC was running the SAM-BA bootloader * (with reserved bits set to 0). */ key = irq_lock(); /* Setup the flash controller. * The bootloader is running @ 48 MHz with * FWS == 2. * When running at 84 MHz, FWS == 4 seems * to be more stable, and allows the board * to boot. */ __EEFC0->fmr = 0x00000400; __EEFC1->fmr = 0x00000400; _ClearFaults(); /* Setup master clock */ clock_init(); /* Disable watchdog timer, not used by system */ __WDT->mr |= WDT_DISABLE; /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
/** * @brief Perform basic hardware initialization at boot. * * This needs to be run from the very beginning. * So the init priority has to be 0 (zero). * * @return 0 */ static int stm32f1_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); _ClearFaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); /* Update CMSIS SystemCoreClock variable (HCLK) */ /* At reset, system core clock is set to 8 MHz from HSI */ SystemCoreClock = 8000000; return 0; }
static int nordicsemi_nrf52_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); #ifdef CONFIG_SOC_NRF52832 nordicsemi_nrf52832_init(); #endif #ifdef CONFIG_SOC_NRF52840 nordicsemi_nrf52840_init(); #endif /* Enable the FPU if the compiler used floating point unit * instructions. Since the FPU consumes energy, remember to * disable FPU use in the compiler if floating point unit * operations are not used in your code. */ #if defined(CONFIG_FLOAT) SCB->CPACR |= (3UL << 20) | (3UL << 22); __DSB(); __ISB(); #endif /* Configure NFCT pins as GPIOs if NFCT is not to be used in * your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, * two GPIOs (see Product Specification to see which ones) * will be reserved for NFC and will not be available as * normal GPIOs. */ #if defined(CONFIG_NFCT_PINS_AS_GPIOS) if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) { NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NVIC_SystemReset(); } #endif _ClearFaults(); /* Setup master clock */ clock_init(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }