/*!
* \cond DOXYGEN_PRIVATE
* \brief Initialization - called from init task, usually for io initialization.
*/
int _bsp_init(void)
{
uint32_t result = MQX_OK;
/** Cache settings **/
_DCACHE_ENABLE(0);
_ICACHE_ENABLE(0);
/* Disable MPU if present on device. This dirty hack is done to workaround missing MPU_DRV_Disable() function in KSDK */
#ifdef MPU_INSTANCE_COUNT
for(int i = 0; i < MPU_INSTANCE_COUNT; i++)
{
MPU_HAL_Disable(g_mpuBase[i]);
}
#endif
/******************************************************************************
Install interrupts for UART driver and setup debug console
******************************************************************************/
#if BSPCFG_ENABLE_IO_SUBSYSTEM
_bsp_nio_stdio_install();
#else /* BSPCFG_ENABLE_IO_SUBSYSTEM */
#if !defined(PEX_MQX_KSDK)
dbg_uart_init();
#endif
#endif /* BSPCFG_ENABLE_IO_SUBSYSTEM */
return result;
}
/** Pre initialization - initializing requested modules for basic run of MQX.
*/
int _bsp_pre_init(void) {
KERNEL_DATA_STRUCT_PTR kernel_data;
uint32_t result;
_mqx_int i;
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MCF548x support functions */
_mcf5441_initialize_support(0);
/*
** Initialize the interrupt handling
*/
_int_set_vector_table(BSP_RAM_INTERRUPT_VECTOR_TABLE);
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize the timer interrupt */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR, _bsp_timer_isr, NULL) == NULL) {
return MQX_TIMER_ISR_INSTALL_FAIL;
} /* Endif */
#if BSPCFG_HAS_SRAM_POOL
/* When kernel data is placed outside of the SRAM memory create new _BSP_sram_pool in the SRAM,
otherwise if kernel data points to SRAM, the _BSP_sram_pool points to system pool. */
if ( (((uint32_t)__INTERNAL_SRAM_BASE) < (uint32_t)BSP_DEFAULT_START_OF_KERNEL_MEMORY) &&
(((uint32_t)BSP_DEFAULT_START_OF_KERNEL_MEMORY) < ((uint32_t)__INTERNAL_SRAM_BASE + (uint32_t)__INTERNAL_SRAM_SIZE)))
{
_BSP_sram_pool = _mem_get_system_pool_id();
}
else
{
_BSP_sram_pool = _mem_create_pool(__SRAM_POOL, (uint32_t)__INTERNAL_SRAM_BASE + (uint32_t)__INTERNAL_SRAM_SIZE - (uint32_t)__SRAM_POOL);
}
#endif
_GET_KERNEL_DATA(kernel_data);
// Initialize the slice timer to interrupt the specified
// number of times per second
kernel_data->TIMER_HW_REFERENCE = _pit_init_freq(BSP_TIMER, BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK/2, FALSE);
_time_set_hwtick_function(_pit_get_hwticks, (void *)BSP_TIMER);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
_pit_unmask_int(BSP_TIMER);
// Initialize and enable the serial UART interrupts
_mcf5441_int_init(BSP_UART0_INT_VECTOR, BSP_UART0_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART2_INT_VECTOR, BSP_UART2_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART4_INT_VECTOR, BSP_UART4_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART6_INT_VECTOR, BSP_UART6_INT_LEVEL, TRUE);
// Install and mask the DMA interrupt handler
/*
_int_install_isr(BSP_ENET_DMA_INTERRUPT, _mcf5445_dma_isr, (void *)0);
_mcf5445_int_init(BSP_ENET_DMA_INTERRUPT, BSP_ENET_DMA_INT_LEVEL, BSP_ENET_DMA_INT_PRIORITY, FALSE);
*/
// Initialize and disable the security engine interrupt
// _mcf54xx_int_init(MCF548x_INT_SEC, BSP_SEC_INT_LEVEL, /*BSP_SEC_INT_PRIORITY, */FALSE);
#if BSP_TRAP_EXCEPTIONS
_int_install_unexpected_isr();
#endif
// Always invalidate the caches even if not enabled. This allows
// us to flush the cache always. If we flush before invalidating
// very bad things happen.
_ICACHE_INVALIDATE();
_DCACHE_INVALIDATE();
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
static const PSP_MMU_INIT_STRUCT mmu_init = {
/* We define the default cacheability of non-ACR mapped regions */
/* as non-cacheable and unbuffered */
MCF54XX_CACR_DDCM(MCF54XX_CACHE_NONCACHEABLE_UNBUFFERED)
};
/* Initialize Cache Control Register CACR */
_mmu_init((void *)&mmu_init);
/* Set up 1 instruction and 1 data ACR in two separate SDRAM areas */
/* Caution: Consider memory map in linker command file before changing regions */
/* Note: Second arg to _mmu_add_region is used in mask value in ACR */
result = _mmu_add_region(__CACHED_CODE_START, __CACHED_CODE_END - __CACHED_CODE_START, PSP_MMU_EXEC_ALLOWED);
if (result != MQX_OK) return result;
result = _mmu_add_region(__CACHED_DATA_START, __CACHED_DATA_END - __CACHED_DATA_START, PSP_MMU_WRITE_THROUGH);
if (result != MQX_OK) return result;
/* Copy ACR table into ACR registers */
_MMU_ENABLE();
/* Enable instruction cache and branch history cache in CACR */
_ICACHE_ENABLE(MCF54XX_CACR_IEC | MCF54XX_CACR_BEC);
/* Enable data cache bit in CACR */
_DCACHE_ENABLE(0);
} /* Endif */
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
__cpp_init();
#endif
return 0;
}