/*******************************************************************************
* Function Name: Cy_MCWDT_Init
****************************************************************************//**
*
* Initializes the MCWDT block.
*
* \param base
* The base pointer to a structure that describes the registers.
*
* \param config
* The pointer to a structure that contains component configuration data.
*
* \return cy_en_mcwdt_status_t
* *base checking result. If the pointer is NULL, returns error.
*
* \note
* This API should not be called when the counters are running. Prior to calling
* this API the counter should be disabled.
*
*******************************************************************************/
cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config)
{
cy_en_mcwdt_status_t ret = CY_MCWDT_BAD_PARAM;
if ((base != NULL) && (config != NULL))
{
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c0ClearOnMatch, config->c0Match));
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c1ClearOnMatch, config->c1Match));
CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(config->c2ToggleBit));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c0Mode));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c1Mode));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c2Mode));
MCWDT_STRUCT_MCWDT_MATCH(base) = _VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, config->c1Match) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, config->c0Match);
MCWDT_STRUCT_MCWDT_CONFIG(base) = _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, config->c2ToggleBit) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2, config->c2Mode) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, config->c0ClearOnMatch) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, config->c1ClearOnMatch) |
(config->c1c2Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk : 0UL) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1, config->c1Mode) |
(config->c0c1Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk : 0UL) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0, config->c0Mode);
ret = CY_MCWDT_SUCCESS;
}
return (ret);
}
/*******************************************************************************
* Function Name: Cy_SysEnableCM4
****************************************************************************//**
*
* Sets vector table base address and enables the Cortex-M4 core.
*
* \note If the CPU is already enabled, it is reset and then enabled.
*
* \param vectorTableOffset The offset of the vector table base address from
* memory address 0x00000000. The offset should be multiple to 1024 bytes.
*
*******************************************************************************/
void Cy_SysEnableCM4(uint32_t vectorTableOffset)
{
uint32_t regValue;
uint32_t interruptState;
uint32_t cpuState;
interruptState = Cy_SaveIRQ();
cpuState = Cy_SysGetCM4Status();
if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
{
Cy_SysResetCM4();
}
CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM4_STATUS_ENABLED;
CPUSS->CM4_PWR_CTL = regValue;
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
Cy_RestoreIRQ(interruptState);
}
/*******************************************************************************
* Function Name: Cy_WDT_Lock
****************************************************************************//**
*
* Locks out configuration changes to the Watchdog Timer register.
*
* After this function is called, the WDT configuration cannot be changed until
* Cy_WDT_Unlock() is called.
*
*******************************************************************************/
void Cy_WDT_Lock(void)
{
uint32_t interruptState;
interruptState = Cy_SysLib_EnterCriticalSection();
SRSS->WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_LOCK, CY_SRSS_WDT_LOCK_BITS);
Cy_SysLib_ExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: Cy_WDT_ClearInterrupt
****************************************************************************//**
*
* Clears the WDT match flag which is set every time the WDT counter reaches a
* WDT match value. Two unserviced interrupts lead to a system reset
* (i.e. at the third match).
*
*******************************************************************************/
void Cy_WDT_ClearInterrupt(void)
{
SRSS->SRSS_INTR = _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1u);
/* Read the interrupt register to ensure that the initial clearing write has
* been flushed out to the hardware.
*/
(void) SRSS->SRSS_INTR;
}
/*******************************************************************************
* Function Name: Cy_DMAC_Descriptor_SetXloopDataCount
****************************************************************************//**
*
* Sets the number of data elements to transfer in the X loop
* for the specified descriptor (for 1D or 2D descriptors only).
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param xCount
* The number of data elements to transfer in the X loop.
*
* \funcusage
* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetNextDescriptor
*
*******************************************************************************/
void Cy_DMAC_Descriptor_SetXloopDataCount(cy_stc_dmac_descriptor_t * descriptor, uint32_t xCount)
{
CY_ASSERT_L1(NULL != descriptor);
cy_en_dmac_descriptor_type_t locDescriptorType = Cy_DMAC_Descriptor_GetDescriptorType(descriptor);
CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != locDescriptorType);
CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(xCount));
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
if (CY_DMAC_SCATTER_TRANSFER == locDescriptorType)
{
descriptor->dst = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, xCount);
}
else
{
descriptor->xSize = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, xCount);
}
}
/*******************************************************************************
* Function Name: Cy_SysTick_SetClockSource
****************************************************************************//**
*
* Sets the clock source for the SysTick counter.
*
* Clears the SysTick count flag if it was set. If the clock source is not ready
* this function call will have no effect. After changing the clock source to the
* low frequency clock, the counter and reload register values will remain
* unchanged so the time to the interrupt will be significantly longer and vice
* versa.
*
* Changing the SysTick clock source and/or its frequency will change
* the interrupt interval and Cy_SysTick_SetReload() should be
* called to compensate this change.
*
* \param clockSource \ref cy_en_systick_clock_source_t Clock source.
*
*******************************************************************************/
void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource)
{
if (clockSource == CY_SYSTICK_CLOCK_SOURCE_CLK_CPU)
{
SYSTICK_CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
}
else
{
CPUSS_SYSTICK_CTL = _VAL2FLD(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, (uint32_t) clockSource);
SYSTICK_CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
}
}
/*******************************************************************************
* Function Name: Cy_SysRetainCM4
****************************************************************************//**
*
* Retains the Cortex-M4 core and exists without waiting for the mode to take
* effect.
*
* \note The retained mode can be entered only from the enabled mode.
*
* \warning Do not call the function while the Cortex-M4 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
*
*******************************************************************************/
void Cy_SysRetainCM4(void)
{
uint32_t interruptState;
uint32_t regValue;
interruptState = Cy_SaveIRQ();
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM4_STATUS_RETAINED;
CPUSS->CM4_PWR_CTL = regValue;
Cy_RestoreIRQ(interruptState);
}
/*******************************************************************************
* Function Name: DynamicEndpointReConfiguration
****************************************************************************//**
*
* Changes endpoint direction (IN -> OUT or OUT -> IN).
* This function is also used to flush IN or OUT endpoint buffer.
* Applicable only when mode is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO.
*
* \param base
* The pointer to the USBFS instance.
*
* \param inDirection
* True - endpoint direction is IN; False - endpoint direction is OUT.
*
* \param endpoint
* The data endpoint number.
*
* \return
* Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t.
*
*******************************************************************************/
cy_en_usbfs_dev_drv_status_t DynamicEndpointReConfiguration(USBFS_Type *base,
bool inDirection,
uint32_t endpoint)
{
cy_en_usbfs_dev_drv_status_t retStatus = CY_USBFS_DEV_DRV_EP_DYN_RECONFIG_TIMEOUT;
uint32_t timeout = DYN_RECONFIG_TIMEOUT;
/* Only enabled endpoint can be re-configured */
if (0U == (USBFS_DEV_EP_ACTIVE(base) & EP2MASK(endpont)))
{
return CY_USBFS_DEV_DRV_BUF_ALLOC_FAILED;
}
/* Request reconfiguration for endpoint */
USBFS_DEV_DYN_RECONFIG(base) = (USBFS_USBDEV_DYN_RECONFIG_EN_Msk |
_VAL2FLD(USBFS_USBDEV_DYN_RECONFIG_EPNO, endpoint));
/* Cypress ID#295549: execute dummy read */
(void) USBFS_DEV_DYN_RECONFIG(base);
/* Wait for dynamic re-configuration completion */
while ((0U == (USBFS_DEV_DYN_RECONFIG(base) & USBFS_USBDEV_DYN_RECONFIG_RDY_STS_Msk)) &&
(timeout > 0U))
{
Cy_SysLib_DelayUs(DYN_RECONFIG_ONE_TICK);
--timeout;
}
/* Verify operation result */
if (timeout > 0U)
{
Cy_USBFS_Dev_Drv_SetEpType(base, inDirection, endpoint);
retStatus = CY_USBFS_DEV_DRV_SUCCESS;
}
/* Complete endpoint reconfiguration: clear request */
USBFS_DEV_DYN_RECONFIG(base) &= ~USBFS_USBDEV_DYN_RECONFIG_EN_Msk;
(void) USBFS_DEV_DYN_RECONFIG(base);
/* Clear register for next re-configuration */
USBFS_DEV_DYN_RECONFIG(base) = 0U;
return retStatus;
}
/*******************************************************************************
* Function Name: Cy_Crypto_Core_V2_Aes_Init
****************************************************************************//**
*
* Sets AES mode and prepares inverse key.
*
* \param base
* The pointer to the CRYPTO instance.
*
* \param key
* The pointer to the encryption/decryption key.
*
* \param keyLength
* \ref cy_en_crypto_aes_key_length_t
*
* \param aesState
* The pointer to the AES state structure allocated by the user. The user
* must not modify anything in this structure.
*
* \return
* \ref cy_en_crypto_status_t
*
*******************************************************************************/
cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Init(CRYPTO_Type *base,
uint8_t const *key,
cy_en_crypto_aes_key_length_t keyLength,
cy_stc_crypto_aes_state_t *aesState)
{
CY_ASSERT_L1(NULL != key);
CY_ASSERT_L1(NULL != aesState);
CY_ASSERT_L3(CY_CRYPTO_IS_KEYLENGTH_VALID(keyLength));
Cy_Crypto_Core_V2_MemSet(base, aesState, 0u, sizeof(cy_stc_crypto_aes_state_t));
aesState->key = (uint8_t *)key;
aesState->keyLength = keyLength;
REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, aesState->keyLength));
return (CY_CRYPTO_SUCCESS);
}
/*******************************************************************************
* Function Name: Cy_DMAC_Channel_Init
****************************************************************************//**
*
* Initializes the DMA channel with a descriptor and other parameters.
*
* \param base
* The pointer to the hardware DMAC block.
*
* \param channel
* A channel number.
*
* \param channelConfig
* The structure that has the initialization information for the
* channel.
*
* \return
* The status /ref cy_en_dmac_status_t.
*
* \funcusage
* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable
*
*******************************************************************************/
cy_en_dmac_status_t Cy_DMAC_Channel_Init(DMAC_Type * base, uint32_t channel, cy_stc_dmac_channel_config_t const * channelConfig)
{
cy_en_dmac_status_t ret = CY_DMAC_BAD_PARAM;
if ((NULL != base) && (CY_DMAC_IS_CH_NR_VALID(channel)) && (NULL != channelConfig) && (NULL != channelConfig->descriptor))
{
CY_ASSERT_L2(CY_DMAC_IS_PRIORITY_VALID(channelConfig->priority));
/* Set the current descriptor */
DMAC_CH_CURR(base, channel) = (uint32_t)channelConfig->descriptor;
/* Set the channel configuration */
DMAC_CH_CTL(base, channel) = _VAL2FLD(DMAC_CH_V2_CTL_PRIO, channelConfig->priority) |
_BOOL2FLD(DMAC_CH_V2_CTL_ENABLED, channelConfig->enable);
ret = CY_DMAC_SUCCESS;
}
return (ret);
}
/*******************************************************************************
* Function Name: Cy_SysResetCM4
****************************************************************************//**
*
* Resets the Cortex-M4 core and waits for the mode to take the effect.
*
* \note The reset mode can not be entered from the retained mode.
*
* \warning Do not call the function while the Cortex-M4 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
*
*******************************************************************************/
void Cy_SysResetCM4(void)
{
uint32_t interruptState;
uint32_t regValue;
interruptState = Cy_SaveIRQ();
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM4_STATUS_RESET;
CPUSS->CM4_PWR_CTL = regValue;
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
Cy_RestoreIRQ(interruptState);
}
/*******************************************************************************
* Function Name: Cy_Crypto_Core_V1_Aes_Init
****************************************************************************//**
*
* Sets AES mode and prepares an inverse key.
*
* \param base
* The pointer to the CRYPTO instance.
*
* \param key
* The pointer to the encryption/decryption key.
*
* \param keyLength
* \ref cy_en_crypto_aes_key_length_t
*
* \param aesState
* The pointer to the AES state structure allocated by the user. The user
* must not modify anything in this structure.
*
* \return
* \ref cy_en_crypto_status_t
*
*******************************************************************************/
cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Init(CRYPTO_Type *base,
uint8_t const *key,
cy_en_crypto_aes_key_length_t keyLength,
cy_stc_crypto_aes_state_t *aesState)
{
aesState->keyLength = keyLength;
/* Set the key mode: 128, 192 or 256 Bit */
REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, (uint32_t)(aesState->keyLength)));
cy_stc_crypto_aes_buffers_t *aesBuffers = (cy_stc_crypto_aes_buffers_t *)(REG_CRYPTO_MEM_BUFF(base));
aesState->buffers = (uint32_t*) aesBuffers;
aesState->key = (uint8_t *)(aesBuffers->key);
aesState->invKey = (uint8_t *)(aesBuffers->keyInv);
Cy_Crypto_Core_V1_MemCpy(base, aesState->key, key, CY_CRYPTO_AES_256_KEY_SIZE);
Cy_Crypto_Core_V1_Aes_InvKey(base, aesState);
return (CY_CRYPTO_SUCCESS);
}
/*******************************************************************************
* Function Name: Cy_TCPWM_PWM_Init
****************************************************************************//**
*
* Initializes the counter in the TCPWM block for the PWM operation.
*
* \param base
* The pointer to a TCPWM instance.
*
* \param cntNum
* The Counter instance number in the selected TCPWM.
*
* \param config
* The pointer to a configuration structure. See \ref cy_stc_tcpwm_pwm_config_t.
*
* \return error / status code. See \ref cy_en_tcpwm_status_t.
*
* \funcusage
* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_Config
* \snippet tcpwm\1.10\pwm\snippet\main.c snippet_Cy_TCPWM_PWM_Init
*
*******************************************************************************/
cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config)
{
cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM;
if ((NULL != base) && (NULL != config))
{
TCPWM_CNT_CTRL(base, cntNum) = ((config->enableCompareSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk : 0UL) |
(config->enablePeriodSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk : 0UL) |
_VAL2FLD(TCPWM_CNT_CTRL_ONE_SHOT, config->runMode) |
_VAL2FLD(TCPWM_CNT_CTRL_UP_DOWN_MODE, config->pwmAlignment) |
_VAL2FLD(TCPWM_CNT_CTRL_MODE, config->pwmMode) |
_VAL2FLD(TCPWM_CNT_CTRL_QUADRATURE_MODE,
(config->invertPWMOut | (config->invertPWMOutN << 1U))) |
(config->killMode << CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS) |
_VAL2FLD(TCPWM_CNT_CTRL_GENERIC, ((CY_TCPWM_PWM_MODE_DEADTIME == config->pwmMode) ?
config->deadTimeClocks : config->clockPrescaler)));
if (CY_TCPWM_PWM_MODE_PSEUDORANDOM == config->pwmMode)
{
TCPWM_CNT_COUNTER(base, cntNum) = CY_TCPWM_CNT_UP_DOWN_INIT_VAL;
TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_PWM_MODE_PR;
}
else
{
if (CY_TCPWM_PWM_LEFT_ALIGN == config->pwmAlignment)
{
TCPWM_CNT_COUNTER(base, cntNum) = CY_TCPWM_CNT_UP_INIT_VAL;
TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_PWM_MODE_LEFT;
}
else if (CY_TCPWM_PWM_RIGHT_ALIGN == config->pwmAlignment)
{
TCPWM_CNT_COUNTER(base, cntNum) = config->period0;
TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_PWM_MODE_RIGHT;
}
else
{
TCPWM_CNT_COUNTER(base, cntNum) = CY_TCPWM_CNT_UP_DOWN_INIT_VAL;
TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM;
}
}
TCPWM_CNT_CC(base, cntNum) = config->compare0;
TCPWM_CNT_CC_BUFF(base, cntNum) = config->compare1;
TCPWM_CNT_PERIOD(base, cntNum) = config->period0;
TCPWM_CNT_PERIOD_BUFF(base, cntNum) = config->period1;
if (CY_TCPWM_INPUT_CREATOR != config->countInput)
{
TCPWM_CNT_TR_CTRL0(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_CAPTURE_SEL, config->swapInput) |
_VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->reloadInput) |
_VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->startInput) |
_VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->killInput) |
_VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->countInput));
}
TCPWM_CNT_TR_CTRL1(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, config->swapInputMode) |
_VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->reloadInputMode) |
_VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, config->startInputMode) |
_VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->killInputMode) |
_VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, config->countInputMode));
TCPWM_CNT_INTR_MASK(base, cntNum) = config->interruptSources;
status = CY_TCPWM_SUCCESS;
}
return(status);
}
/*******************************************************************************
* Function Name: Cy_DMAC_Descriptor_Init
****************************************************************************//**
*
* Initializes the descriptor structure in SRAM from a pre-initialized
* configuration structure.
* This function initializes only the descriptor and not the channel.
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param config
* This is a configuration structure that has all initialization information for
* the descriptor.
*
* \return
* The status /ref cy_en_dmac_status_t.
*
* \funcusage
* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable
*
*******************************************************************************/
cy_en_dmac_status_t Cy_DMAC_Descriptor_Init(cy_stc_dmac_descriptor_t * descriptor, const cy_stc_dmac_descriptor_config_t * config)
{
cy_en_dmac_status_t ret = CY_DMAC_BAD_PARAM;
if ((NULL != descriptor) && (NULL != config))
{
CY_ASSERT_L3(CY_DMAC_IS_RETRIGGER_VALID(config->retrigger));
CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->interruptType));
CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerOutType));
CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerInType));
CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->srcTransferSize));
CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->dstTransferSize));
CY_ASSERT_L3(CY_DMAC_IS_CHANNEL_STATE_VALID(config->channelState));
CY_ASSERT_L3(CY_DMAC_IS_DATA_SIZE_VALID(config->dataSize));
CY_ASSERT_L3(CY_DMAC_IS_TYPE_VALID(config->descriptorType));
descriptor->ctl =
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT, config->retrigger) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_INTR_TYPE, config->interruptType) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE, config->triggerOutType) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, config->triggerInType) |
_BOOL2FLD(DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH, config->dataPrefetch) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE, config->srcTransferSize) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE, config->dstTransferSize) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_CH_DISABLE, config->channelState) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_DATA_SIZE, config->dataSize) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, config->descriptorType);
descriptor->src = (uint32_t)config->srcAddress;
switch(config->descriptorType)
{
case CY_DMAC_SINGLE_TRANSFER:
{
descriptor->dst = (uint32_t)config->dstAddress;
descriptor->xSize = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_1D_TRANSFER:
{
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(config->xCount));
descriptor->dst = (uint32_t)config->dstAddress;
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->xSize = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xIncr = _VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_SRC_X, config->srcXincrement) |
_VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_DST_X, config->dstXincrement);
descriptor->ySize = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_2D_TRANSFER:
{
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(config->xCount));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcYincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstYincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(config->yCount));
descriptor->dst = (uint32_t)config->dstAddress;
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->xSize = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xIncr = _VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_SRC_X, config->srcXincrement) |
_VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_DST_X, config->dstXincrement);
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->ySize = _VAL2FLD(DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT, config->yCount - 1UL);
descriptor->yIncr = _VAL2FLD(DMAC_CH_V2_DESCR_Y_INCR_SRC_Y, config->srcYincrement) |
_VAL2FLD(DMAC_CH_V2_DESCR_Y_INCR_DST_Y, config->dstYincrement);
descriptor->nextPtr = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_MEMORY_COPY:
{
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcXincrement));
descriptor->dst = (uint32_t)config->dstAddress;
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->xSize = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xIncr = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_SCATTER_TRANSFER:
{
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->dst = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xSize = (uint32_t)config->nextDescriptor;
break;
}
default:
{
/* An unsupported type of a descriptor */
break;
}
}
ret = CY_DMAC_SUCCESS;
}
return ret;
}
