void init_CLock()
{
__GPIOA_CLK_ENABLE();
__GPIOB_CLK_ENABLE();
__GPIOC_CLK_ENABLE();
__SYSCFG_CLK_ENABLE();
__ETH_CLK_ENABLE();
__HAL_RCC_ETHMAC_CLK_ENABLE();
}
error_t stm32f4x7EthInit(NetInterface *interface)
{
error_t error;
//Debug message
TRACE_INFO("Initializing STM32F4x7 Ethernet MAC...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//GPIO configuration
stm32f4x7EthInitGpio(interface);
#if defined(USE_HAL_DRIVER)
//Enable Ethernet MAC clock
__HAL_RCC_ETHMAC_CLK_ENABLE();
__HAL_RCC_ETHMACTX_CLK_ENABLE();
__HAL_RCC_ETHMACRX_CLK_ENABLE();
//Reset Ethernet MAC peripheral
__HAL_RCC_ETHMAC_FORCE_RESET();
__HAL_RCC_ETHMAC_RELEASE_RESET();
#else
//Enable Ethernet MAC clock
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC |
RCC_AHB1Periph_ETH_MAC_Tx | RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
//Reset Ethernet MAC peripheral
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
#endif
//Perform a software reset
ETH->DMABMR |= ETH_DMABMR_SR;
//Wait for the reset to complete
while(ETH->DMABMR & ETH_DMABMR_SR);
//Adjust MDC clock range depending on HCLK frequency
ETH->MACMIIAR = ETH_MACMIIAR_CR_Div102;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Use default MAC configuration
ETH->MACCR = ETH_MACCR_ROD;
//Set the MAC address
ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
ETH->MACA0HR = interface->macAddr.w[2];
//Initialize hash table
ETH->MACHTLR = 0;
ETH->MACHTHR = 0;
//Configure the receive filter
ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_HM;
//Disable flow control
ETH->MACFCR = 0;
//Enable store and forward mode
ETH->DMAOMR = ETH_DMAOMR_RSF | ETH_DMAOMR_TSF;
//Configure DMA bus mode
ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_USP | ETH_DMABMR_RDP_1Beat |
ETH_DMABMR_RTPR_1_1 | ETH_DMABMR_PBL_1Beat | ETH_DMABMR_EDE;
//Initialize DMA descriptor lists
stm32f4x7EthInitDmaDesc(interface);
//Prevent interrupts from being generated when the transmit statistic
//counters reach half their maximum value
ETH->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM;
//Prevent interrupts from being generated when the receive statistic
//counters reach half their maximum value
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
//Disable MAC interrupts
ETH->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM;
//Enable the desired DMA interrupts
ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
//Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
NVIC_SetPriorityGrouping(STM32F4X7_ETH_IRQ_PRIORITY_GROUPING);
//Configure Ethernet interrupt priority
NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(STM32F4X7_ETH_IRQ_PRIORITY_GROUPING,
STM32F4X7_ETH_IRQ_GROUP_PRIORITY, STM32F4X7_ETH_IRQ_SUB_PRIORITY));
//Enable MAC transmission and reception
ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
//Enable DMA transmission and reception
ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
//Accept any packets from the upper layer
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
