/* start simulation, program loaded, processor precise state initialized */
void
sim_main(void)
{
md_inst_t inst;
register md_addr_t addr;
enum md_opcode op;
register int is_write;
enum md_fault_type fault;
fprintf(stderr, "sim: ** starting functional simulation **\n");
/* set up initial default next PC */
regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
/* check for DLite debugger entry condition */
if (dlite_check_break(regs.regs_PC, /* !access */0, /* addr */0, 0, 0))
dlite_main(regs.regs_PC - sizeof(md_inst_t),
regs.regs_PC, sim_num_insn, ®s, mem);
while (TRUE)
{
/* maintain $r0 semantics */
regs.regs_R[MD_REG_ZERO] = 0;
#ifdef TARGET_ALPHA
regs.regs_F.d[MD_REG_ZERO] = 0.0;
#endif /* TARGET_ALPHA */
/* get the next instruction to execute */
inst = __UNCHK_MEM_READ(mem, regs.regs_PC, md_inst_t);
/* keep an instruction count */
sim_num_insn++;
/* set default reference address and access mode */
addr = 0; is_write = FALSE;
/* set default fault - none */
fault = md_fault_none;
/* decode the instruction */
MD_SET_OPCODE(op, inst);
/* execute the instruction */
switch (op)
{
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
case OP: \
SYMCAT(OP,_IMPL); \
break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
case OP: \
panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT) \
{ fault = (FAULT); break; }
#include "machine.def"
default:
panic("attempted to execute a bogus opcode");
}
if (fault != md_fault_none)
fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
if (verbose)
{
myfprintf(stderr, "%10n [xor: 0x%08x] @ 0x%08p: ",
sim_num_insn, md_xor_regs(®s), regs.regs_PC);
md_print_insn(inst, regs.regs_PC, stderr);
if (MD_OP_FLAGS(op) & F_MEM)
myfprintf(stderr, " mem: 0x%08p", addr);
fprintf(stderr, "\n");
/* fflush(stderr); */
}
if (MD_OP_FLAGS(op) & F_MEM)
{
sim_num_refs++;
if (MD_OP_FLAGS(op) & F_STORE)
is_write = TRUE;
}
/* check for DLite debugger entry condition */
if (dlite_check_break(regs.regs_NPC,
is_write ? ACCESS_WRITE : ACCESS_READ,
addr, sim_num_insn, sim_num_insn))
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
/* go to the next instruction */
regs.regs_PC = regs.regs_NPC;
regs.regs_NPC += sizeof(md_inst_t);
/* finish early? */
if (max_insts && sim_num_insn >= max_insts)
return;
}
}
/* start simulation, program loaded, processor precise state initialized */
void
sim_main(void)
{
md_inst_t inst;
register md_addr_t addr;
enum md_opcode op;
register bool_t is_write;
enum md_fault_type fault;
/* set up initial default next PC */
regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
/* check for DLite debugger entry condition */
if (dlite_check_break(regs.regs_PC, /* !access */0, /* addr */0, 0, 0))
dlite_main(regs.regs_PC - sizeof(md_inst_t), regs.regs_PC,
sim_num_insn, ®s, mem);
/* fast forward simulator loop, performs functional simulation for
FASTFWD_COUNT insts, then turns on performance (timing) simulation */
if (fastfwd_count > 0)
{
int icount;
fprintf(stderr, "sim: ** fast forwarding %d insts **\n", fastfwd_count);
fastfwding = TRUE;
for (icount=0; icount < fastfwd_count; icount++)
{
/* maintain $r0 semantics */
regs.regs_R[MD_REG_ZERO] = 0;
#ifdef TARGET_ALPHA
regs.regs_F.d[MD_REG_ZERO] = 0.0;
#endif /* TARGET_ALPHA */
/* get the next instruction to execute */
inst = __UNCHK_MEM_READ(mem, regs.regs_PC, md_inst_t);
/* set default reference address */
addr = 0; is_write = FALSE;
/* set default fault - none */
fault = md_fault_none;
/* decode the instruction */
MD_SET_OPCODE(op, inst);
/* execute the instruction */
switch (op)
{
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
case OP: \
SYMCAT(OP,_IMPL); \
break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
case OP: \
panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#undef DECLARE_FAULT
#define DECLARE_FAULT(FAULT) \
{ fault = (FAULT); break; }
#include "machine.def"
default:
panic("attempted to execute a bogus opcode");
}
if (fault != md_fault_none)
fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
/* update memory access stats */
if (MD_OP_FLAGS(op) & F_MEM)
{
if (MD_OP_FLAGS(op) & F_STORE)
is_write = TRUE;
}
/* check for DLite debugger entry condition */
if (dlite_check_break(regs.regs_NPC,
is_write ? ACCESS_WRITE : ACCESS_READ,
addr, sim_num_insn, sim_num_insn))
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
/* go to the next instruction */
regs.regs_PC = regs.regs_NPC;
regs.regs_NPC += sizeof(md_inst_t);
}
}
fastfwding = FALSE;
if (trace_fd != NULL)
{
fprintf(stderr, "sim: writing EIO file initial checkpoint...\n");
if (eio_write_chkpt(®s, mem, trace_fd) != -1)
panic("checkpoint code is broken");
}
fprintf(stderr, "sim: ** starting functional simulation **\n");
/* set up initial default next PC */
regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
while (TRUE)
{
/* maintain $r0 semantics */
regs.regs_R[MD_REG_ZERO] = 0;
#ifdef TARGET_ALPHA
regs.regs_F.d[MD_REG_ZERO] = 0.0;
#endif /* TARGET_ALPHA */
/* check if checkpoint should be generated here... */
if (chkpt_active
&& !range_cmp_range1(&chkpt_range, regs.regs_NPC,
sim_num_insn, sim_num_insn))
{
fprintf(stderr, "sim: writing checkpoint file `%s' @ inst %.0f...\n",
chkpt_fname, (double)sim_num_insn);
/* write the checkpoint file */
eio_write_chkpt(®s, mem, chkpt_fd);
/* close the checkpoint file */
eio_close(chkpt_fd);
/* exit jumps to the target set in main() */
longjmp(sim_exit_buf, /* exitcode + fudge */0+1);
}
/* get the next instruction to execute */
inst = __UNCHK_MEM_READ(mem, regs.regs_PC, md_inst_t);
/* keep an instruction count */
sim_num_insn++;
/* set default reference address and access mode */
addr = 0; is_write = FALSE;
/* set default fault - none */
fault = md_fault_none;
/* decode the instruction */
MD_SET_OPCODE(op, inst);
/* execute the instruction */
switch (op)
{
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
case OP: \
SYMCAT(OP,_IMPL); \
break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
case OP: \
panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT) \
{ fault = (FAULT); break; }
#include "machine.def"
default:
panic("bogus opcode");
}
if (fault != md_fault_none)
fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
if (MD_OP_FLAGS(op) & F_MEM)
{
sim_num_refs++;
if (MD_OP_FLAGS(op) & F_STORE)
is_write = TRUE;
}
/* check for DLite debugger entry condition */
if (dlite_check_break(regs.regs_NPC,
is_write ? ACCESS_WRITE : ACCESS_READ,
addr, sim_num_insn, sim_num_insn))
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
/* go to the next instruction */
regs.regs_PC = regs.regs_NPC;
regs.regs_NPC += sizeof(md_inst_t);
/* finish early? */
if (max_insts && sim_num_insn >= max_insts)
return;
}
}
/* start simulation, program loaded, processor precise state initialized */
void
sim_main(void)
{
#ifdef USE_JUMP_TABLE
/* the jump table employs GNU GCC label extensions to construct an array
of pointers to instruction implementation code, the simulator then uses
the table to lookup the location of instruction's implementing code, a
GNU GCC `goto' extension is then used to jump to the inst's implementing
code through the op_jump table; as a result, there is no need for
a main simulator loop, which eliminates one branch from the simulator
interpreter - crazy, no!?!? */
/* instruction jump table, this code is GNU GCC specific */
static void *op_jump[/* max opcodes */] = {
&&opcode_NA, /* NA */
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
&&opcode_##OP,
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
&&opcode_##OP,
#define CONNECT(OP)
#include "machine.def"
};
#endif /* USE_JUMP_TABLE */
/* register allocate instruction buffer */
register md_inst_t inst;
/* decoded opcode */
register enum md_opcode op;
fprintf(stderr, "sim: ** starting *fast* functional simulation **\n");
/* must have natural byte/word ordering */
if (sim_swap_bytes || sim_swap_words)
fatal("sim: *fast* functional simulation cannot swap bytes or words");
#ifdef USE_JUMP_TABLE
regs.regs_NPC = regs.regs_PC;
/* load instruction */
MD_FETCH_INST(inst, mem, regs.regs_NPC);
/* jump to instruction implementation */
MD_SET_OPCODE(op, inst);
goto *op_jump[op];
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
opcode_##OP: \
/* maintain $r0 semantics */ \
regs.regs_R[MD_REG_ZERO] = 0; \
ZERO_FP_REG(); \
\
/* keep an instruction count */ \
INC_INSN_CTR(); \
\
/* locate next instruction */ \
regs.regs_PC = regs.regs_NPC; \
\
/* set up default next PC */ \
regs.regs_NPC += sizeof(md_inst_t); \
\
/* execute the instruction */ \
SYMCAT(OP,_IMPL); \
\
/* get the next instruction */ \
MD_FETCH_INST(inst, mem, regs.regs_NPC); \
\
/* jump to instruction implementation */ \
MD_SET_OPCODE(op, inst); \
goto *op_jump[op];
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
opcode_##OP: \
panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT) \
{ /* uncaught... */break; }
#include "machine.def"
opcode_NA:
panic("attempted to execute a bogus opcode");
/* should not get here... */
panic("exited sim-fast main loop");
#else /* !USE_JUMP_TABLE */
/* set up initial default next PC */
regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
while (TRUE)
{
/* maintain $r0 semantics */
regs.regs_R[MD_REG_ZERO] = 0;
#ifdef TARGET_ALPHA
regs.regs_F.d[MD_REG_ZERO] = 0.0;
#endif /* TARGET_ALPHA */
/* keep an instruction count */
#ifndef NO_INSN_COUNT
sim_num_insn++;
#endif /* !NO_INSN_COUNT */
#ifdef TARGET_ALPHA
/* load predecoded instruction */
op = (enum md_opcode)__UNCHK_MEM_READ(dec, regs.regs_PC << 1, word_t);
inst =
__UNCHK_MEM_READ(dec, (regs.regs_PC << 1)+sizeof(word_t), md_inst_t);
#else /* !TARGET_ALPHA */
/* load instruction */
MD_FETCH_INST(inst, mem, regs.regs_PC);
/* decode the instruction */
MD_SET_OPCODE(op, inst);
#endif
/* execute the instruction */
switch (op)
{
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
case OP: \
SYMCAT(OP,_IMPL); \
break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
case OP: \
panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT) \
{ /* uncaught... */break; }
#include "machine.def"
default:
panic("attempted to execute a bogus opcode");
}
/* execute next instruction */
regs.regs_PC = regs.regs_NPC;
regs.regs_NPC += sizeof(md_inst_t);
}
#endif /* USE_JUMP_TABLE */
}
