static int cgm_read_proc (char *page, char **start, off_t off,
int count, int *eof, void *data)
{
int len = 0;
unsigned int cppcr = REG_CPM_CPPCR; /* PLL Control Register */
unsigned int cpccr = REG_CPM_CPCCR; /* Clock Control Register */
unsigned int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
unsigned int od[4] = {1, 2, 2, 4};
len += sprintf (page+len, "CPPCR : 0x%08x\n", cppcr);
len += sprintf (page+len, "CPCCR : 0x%08x\n", cpccr);
len += sprintf (page+len, "PLL : %s\n",
(cppcr & CPM_CPPCR_PLLEN) ? "ON" : "OFF");
len += sprintf (page+len, "m:n:o : %d:%d:%d\n",
__cpm_get_pllm() + 2,
__cpm_get_plln() + 2,
od[__cpm_get_pllod()]
);
len += sprintf (page+len, "C:H:M:P : %d:%d:%d:%d\n",
div[__cpm_get_cdiv()],
div[__cpm_get_hdiv()],
div[__cpm_get_mdiv()],
div[__cpm_get_pdiv()]
);
len += sprintf (page+len, "PLL Freq : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pllout()));
len += sprintf (page+len, "CCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_cclk()));
len += sprintf (page+len, "HCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_hclk()));
len += sprintf (page+len, "MCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mclk()));
len += sprintf (page+len, "PCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pclk()));
len += sprintf (page+len, "LCDCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_lcdclk()));
len += sprintf (page+len, "PIXCLK : %3d.%02d KHz\n", TO_KHZ(__cpm_get_pixclk()));
len += sprintf (page+len, "I2SCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_i2sclk()));
len += sprintf (page+len, "USBCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_usbclk()));
len += sprintf (page+len, "MSC0CLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mscclk(0)));
len += sprintf (page+len, "MSC1CLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mscclk(1)));
len += sprintf (page+len, "EXTALCLK0 : %3d.%02d MHz\n", TO_MHZ(__cpm_get_extalclk0()));
len += sprintf (page+len, "EXTALCLK(by CPM): %3d.%02d MHz\n", TO_MHZ(__cpm_get_extalclk()));
len += sprintf (page+len, "RTCCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_rtcclk()));
return len;
}
static void __init sysclocks_setup(void)
{
#ifndef CONFIG_JZ4730_URANUS
jz_clocks.iclk = __cpm_get_iclk();
jz_clocks.sclk = __cpm_get_sclk();
jz_clocks.mclk = __cpm_get_mclk();
jz_clocks.pclk = __cpm_get_pclk();
jz_clocks.devclk = __cpm_get_devclk();
jz_clocks.rtcclk = __cpm_get_rtcclk();
jz_clocks.uartclk = __cpm_get_uartclk();
jz_clocks.lcdclk = __cpm_get_lcdclk();
jz_clocks.pixclk = __cpm_get_pixclk();
jz_clocks.usbclk = __cpm_get_usbclk();
jz_clocks.i2sclk = __cpm_get_i2sclk();
jz_clocks.mscclk = __cpm_get_mscclk();
#else /* URANUS FPGA */
#define FPGACLK 8000000
jz_clocks.iclk = FPGACLK;
jz_clocks.sclk = FPGACLK;
jz_clocks.mclk = FPGACLK;
jz_clocks.devclk = FPGACLK;
jz_clocks.rtcclk = FPGACLK;
jz_clocks.uartclk = FPGACLK;
jz_clocks.pixclk = FPGACLK;
jz_clocks.lcdclk = FPGACLK;
jz_clocks.usbclk = FPGACLK;
jz_clocks.i2sclk = FPGACLK;
jz_clocks.mscclk = FPGACLK;
#endif
printk("CPU clock: %dMHz, System clock: %dMHz, Memory clock: %dMHz, Peripheral clock: %dMHz\n",
(jz_clocks.iclk + 500000) / 1000000,
(jz_clocks.sclk + 500000) / 1000000,
(jz_clocks.mclk + 500000) / 1000000,
(jz_clocks.pclk + 500000) / 1000000);
}
static void jz_fb_hw_set_pixclock(struct jz_fb_ctrl *ctrl)
{
struct jz_fb_ot_info *ot = ctrl->ot;
struct jz_fb_panel_info *panel = ot->config->panel;
unsigned int pixclock, refresh_rate;
unsigned int w, h;
unsigned int v;
D("Called.");
refresh_rate = panel->fclk;
if (ot->use_tve) {
pixclock = 27000000;
}else{
if ((panel->lcd_cfg & LCD_CFG_MODE_MASK) == LCD_CFG_MODE_SERIAL_TFT) {
/* serial mode: Hsync period = 3*Width_Pixel */
w = (panel->w * 3 + panel->hsw + panel->elw + panel->blw);
h = (panel->h + panel->vsw + panel->efw + panel->bfw);
pixclock = w * h * refresh_rate;
}else {
w = (panel->w + panel->hsw + panel->elw + panel->blw);
h = (panel->h + panel->vsw + panel->efw + panel->bfw);
pixclock = w * h * refresh_rate;
}
}
ctrl->pixclock = pixclock;
/* ------------ HW: Set LCD Controller ---------------- */
__cpm_stop_lcd();
if (ot->use_tve) {
REG_CPM_LPCDR |= CPM_LPCDR_LTCS;
__cpm_select_pixclk_tve();
}else{
REG_CPM_LPCDR &= ~CPM_LPCDR_LTCS;
__cpm_select_pixclk_lcd();
}
v = __cpm_get_pllout2() / pixclock;
v--;
__cpm_set_pixdiv(v);
#if defined(CONFIG_SOC_JZ4750) /* Jz4750D don't use LCLK */
v = pixclock * 3 ; /* LCDClock > 2.5*Pixclock */
v = (__cpm_get_pllout()) / v;
if (v > 0x1f) {
printk("lcd clock divide is too large, set it to 0x1f\n");
v = 0x1f;
}
__cpm_set_ldiv(v);
#endif
REG_CPM_CPCCR |= CPM_CPCCR_CE; /* update divide */
jz_clocks.pixclk = __cpm_get_pixclk();
#if defined(CONFIG_SOC_JZ4750) /* Jz4750D don't use LCLK */
jz_clocks.lcdclk = __cpm_get_lcdclk();
I("LCD Controller Clock: %dMHz.", jz_clocks.lcdclk / 1000 / 1000);
#endif
I("Pixel Clock: %dMHz.", pixclock / 1000 / 1000);
__cpm_start_lcd();
mdelay(1);
return;
}
