void __init plat_mem_setup(void)
{
unsigned long fdt_start;
set_io_port_base(KSEG1);
/* Get the position of the FDT passed by the bootloader */
fdt_start = fw_getenvl("fdt_start");
if (fdt_start)
__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
#ifdef CONFIG_BUILTIN_DTB
else
__dt_setup_arch(__dtb_start);
#endif
ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE);
ath79_detect_sys_type();
ath79_ddr_ctrl_init();
if (mips_machtype != ATH79_MACH_GENERIC_OF)
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
_machine_restart = ath79_restart;
_machine_halt = ath79_halt;
pm_power_off = ath79_halt;
}
void __init plat_mem_setup(void)
{
unsigned long fdt_start;
set_io_port_base(KSEG1);
/* Get the position of the FDT passed by the bootloader */
fdt_start = fw_getenvl("fdt_start");
if (fdt_start)
__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
else if (fw_passed_dtb)
__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
if (mips_machtype != ATH79_MACH_GENERIC_OF) {
ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE);
ath79_detect_sys_type();
ath79_ddr_ctrl_init();
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
/* OF machines should use the reset driver */
_machine_restart = ath79_restart;
}
_machine_halt = ath79_halt;
pm_power_off = ath79_halt;
}
void __init plat_mem_setup(void)
{
if (fw_arg0 != -2)
panic("device tree not present");
if (fw_arg1 >= CKSEG0)
__dt_setup_arch((void *)fw_arg1);
else
__dt_setup_arch(phys_to_virt(fw_arg1));
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
plat_setup_iocoherency();
}
void __init plat_mem_setup(void)
{
void *dtb;
const struct bmips_quirk *q;
set_io_port_base(0);
ioport_resource.start = 0;
ioport_resource.end = ~0;
/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
dtb = phys_to_virt(fw_arg2);
else if (fw_arg0 == -2) /* UHI interface */
dtb = (void *)fw_arg1;
else if (__dtb_start != __dtb_end)
dtb = (void *)__dtb_start;
else
panic("no dtb found");
__dt_setup_arch(dtb);
for (q = bmips_quirk_list; q->quirk_fn; q++) {
if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
q->compatible)) {
q->quirk_fn();
}
}
}
void __init plat_mem_setup(void)
{
void *dtb;
dtb = (void *)get_fdtaddr();
if (!dtb) {
pr_err("pic32: no DTB found.\n");
return;
}
/*
* Load the builtin device tree. This causes the chosen node to be
* parsed resulting in our memory appearing.
*/
__dt_setup_arch(dtb);
pr_info("Found following command lines\n");
pr_info(" boot_command_line: %s\n", boot_command_line);
pr_info(" arcs_cmdline : %s\n", arcs_cmdline);
#ifdef CONFIG_CMDLINE_BOOL
pr_info(" builtin_cmdline : %s\n", CONFIG_CMDLINE);
#endif
if (dtb != __dtb_start)
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
#ifdef CONFIG_EARLY_PRINTK
fw_init_early_console(-1);
#endif
pic32_config_init();
}
void __init plat_mem_setup(void)
{
void *fdt = plat_get_fdt();
fdt = sead3_dt_shim(fdt);
__dt_setup_arch(fdt);
}
void __init plat_mem_setup(void)
{
/*
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
__dt_setup_arch(&__dtb_start);
}
void __init plat_mem_setup(void)
{
/* allow command line/bootloader env to override memory size in DT */
parse_memsize_param();
/*
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
__dt_setup_arch(&__dtb_start);
}
void __init plat_mem_setup(void)
{
ioport_resource.start = IOPORT_RESOURCE_START;
ioport_resource.end = IOPORT_RESOURCE_END;
iomem_resource.start = IOMEM_RESOURCE_START;
iomem_resource.end = IOMEM_RESOURCE_END;
set_io_port_base((unsigned long) KSEG1);
/*
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
__dt_setup_arch(&__dtb_start);
}
void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1);
/*
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
__dt_setup_arch(&__dtb_start);
if (soc_info.mem_size)
add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
BOOT_MEM_RAM);
else
detect_memory_region(soc_info.mem_base,
soc_info.mem_size_min * SZ_1M,
soc_info.mem_size_max * SZ_1M);
}
void __init device_tree_init(void)
{
unsigned long base, size;
void *fdt_copy;
set_io_port_base(KSEG1);
/*
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
printk ("DTB: device_tree_init - DBG\n");
__dt_setup_arch(&__image_dtb);
printk ("DTB: device_tree_init - after __dt_setup_arch - DBG\n");
if (!initial_boot_params)
return;
printk ("DTB: device_tree_init - initial_boot_params - DBG\n");
base = virt_to_phys((void *)initial_boot_params);
size = be32_to_cpu(initial_boot_params->totalsize);
/* Before we do anything, lets reserve the dt blob */
reserve_bootmem(base, size, BOOTMEM_DEFAULT);
/* The strings in the flattened tree are referenced directly by the
* device tree, so copy the flattened device tree from init memory
* to regular memory.
*/
fdt_copy = alloc_bootmem(size);
memcpy(fdt_copy, initial_boot_params, size);
initial_boot_params = fdt_copy;
unflatten_device_tree();
/* free the space reserved for the dt blob */
//free_bootmem(base, size);
printk ("DTB: device_tree_init - end - DBG\n");
}
void __init plat_mem_setup(void)
{
void *dtb;
ioport_resource.start = IOPORT_RESOURCE_START;
ioport_resource.end = IOPORT_RESOURCE_END;
iomem_resource.start = IOMEM_RESOURCE_START;
iomem_resource.end = IOMEM_RESOURCE_END;
set_io_port_base((unsigned long) KSEG1);
if (fw_arg0 == -2) /* UHI interface */
dtb = (void *)fw_arg1;
else if (__dtb_start != __dtb_end)
dtb = (void *)__dtb_start;
else
panic("no dtb found");
/*
* Load the devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
__dt_setup_arch(dtb);
}
void __init xlp_early_init_devtree(void)
{
__dt_setup_arch(xlp_fdt_blob);
}
void __init plat_mem_setup(void)
{
__dt_setup_arch(__dtb_start);
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
}
