static inline int
is_avx_supported(void)
{
unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0;
__get_cpuid(1, &eax, &ebx, &ecx, &edx);
return ecx & bit_AVX ? 1 : 0;
}
/// Checks which instruction set extensions are supported by the CPU.
uint detectCPUextensions(void)
{
/// If building for a 64bit system (no Itanium) and the user wants optimizations.
/// Return the OR of SUPPORT_{MMX,SSE,SSE2}. 11001 or 0x19.
/// Keep the _dwDisabledISA test (2 more operations, could be eliminated).
#if ((defined(__GNUC__) && defined(__x86_64__)) \
|| defined(_M_X64)) \
&& defined(SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS)
return 0x19 & ~_dwDisabledISA;
/// If building for a 32bit system and the user wants optimizations.
/// Keep the _dwDisabledISA test (2 more operations, could be eliminated).
#elif ((defined(__GNUC__) && defined(__i386__)) \
|| defined(_M_IX86)) \
&& defined(SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS)
if (_dwDisabledISA == 0xffffffff) return 0;
uint res = 0;
#if !defined(__GNUC__)
// Window / VS version of cpuid. Notice that Visual Studio 2005 or later required
// for __cpuid intrinsic support.
int reg[4] = {-1};
// Check if no cpuid support.
__cpuid(reg,0);
if ((unsigned int)reg[0] == 0) return 0; // always disable extensions.
__cpuid(reg,1);
if ((unsigned int)reg[3] & bit_MMX) res = res | SUPPORT_MMX;
if ((unsigned int)reg[3] & bit_SSE) res = res | SUPPORT_SSE;
if ((unsigned int)reg[3] & bit_SSE2) res = res | SUPPORT_SSE2;
#elif defined(HAVE_CPUID_H)
// GCC version of cpuid. Requires GCC 4.3.0 or later for __cpuid intrinsic support.
uint eax, ebx, ecx, edx; // unsigned int is the standard type. uint is defined by the compiler and not guaranteed to be portable.
// Check if no cpuid support.
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) return 0; // always disable extensions.
if (edx & bit_MMX) res = res | SUPPORT_MMX;
if (edx & bit_SSE) res = res | SUPPORT_SSE;
if (edx & bit_SSE2) res = res | SUPPORT_SSE2;
#else
// Compatible with GCC but no cpuid.h.
return 0;
#endif
return res & ~_dwDisabledISA;
#else
/// One of these is true:
/// 1) We don't want optimizations.
/// 2) Using an unsupported compiler.
/// 3) Running on a non-x86 platform.
return 0;
#endif
}
int read_cpuid()
{
uint32_t key = 1; //processor features
uint32_t proc_info = 0;
uint32_t model;
uint32_t family;
uint32_t ext_model;
uint32_t ext_family;
uint32_t ebx, ecx, edx;
const uint32_t model_mask = 0xF0;
const uint32_t family_mask = 0xF00;
const uint32_t extended_model_mask = 0xF0000;
const uint32_t extended_family_mask = 0xFF00000;
__get_cpuid(key, &proc_info, &ebx, &ecx, &edx);
model = (proc_info & model_mask) >> 4;
family = (proc_info & family_mask) >> 8;
ext_model = (proc_info & extended_model_mask) >> 16;
ext_family = (proc_info & extended_family_mask)>> 20;
if (family == 6) {
model+=(ext_model << 4);
}
else if (family == 15) {
model+=(ext_model << 4);
family+=ext_family;
}
return ((family << 8) + model);
}
static uint64_t get_cpuid_features(void)
{
uint32_t tmp, edx, ecx;
if (__get_cpuid(1, &tmp, &tmp, &ecx, &edx))
return ((((uint64_t)ecx) << 32) ^ edx);
return 0;
}
int main(void)
{
double arr[1000];
double a, b;
int i;
#ifdef __i386__
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (!(edx & bit_SSE2))
return 0;
#endif
for (i = 0; i < 1000; i++)
arr[i] = 4294967296.0 + (double)i;
a = arr[0];
b = (unsigned int)((unsigned long long int)a % 4294967296ULL);
if (b >= 4294967296.0)
abort ();
return 0;
}
int
main(void)
{
unsigned int a, b, c, d;
return __get_cpuid(0, &a, &b, &c, &d);
}
static unsigned int checkCPUFeatures() {
unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0;
unsigned int features = 0;
__get_cpuid(1, &eax, &ebx, &ecx, &edx);
if( (edx & (1 << 25)) != 0 ) {
features |= kCPUFeature_SSE;
}
if( (edx & (1 << 26)) != 0 ) {
features |= kCPUFeature_SSE2;
}
if( (ecx & (1 << 0)) != 0 ) {
features |= kCPUFeature_SSE3;
}
if( (ecx & (1 << 9)) != 0 ) {
features |= kCPUFeature_SSE3_S;
}
if( (ecx & (1 << 19)) != 0 ) {
features |= kCPUFeature_SSE4_1;
}
if( (ecx & (1 << 20)) != 0 ) {
features |= kCPUFeature_SSE4_2;
}
if( (ecx & (1 << 28)) != 0 && (ecx & (1 << 27)) != 0 && (ecx & (1 << 26)) != 0 ) {
xgetbv(0, &eax, &edx);
if( (eax & 6) == 6 ) {
features |= kCPUFeature_AVX;
}
}
return features;
}
void test_sse1_feature(void)
{
unsigned int eax, ebx, ecx, edx;
unsigned int extensions, sig;
int result, sse1_available;
/* call __get_cpuid: there will be bits set in ecx, edx for */
/* the intel-defined SSE1, SSEn features. */
result = __get_cpuid (FUNC_FEATURES, &eax, &ebx, &ecx, &edx);
if (-1 == result)
{
fprintf(stderr, "Fatal Error: can't get CPU features\n");
exit(-1);
}
else
{
sse1_available = (bit_SSE & edx);
if (0 == sse1_available)
{
fprintf(stderr, "Error: SSE1 features not available\n");
fprintf(stderr, "Had this been an actual program, we'd fall ");
fprintf(stderr, "back to a non-SSE1 implementation\n");
exit(-1);
}
else
{
fprintf(stderr, "SSE1 features ARE available\n");
}
}
}
static int detect_vm_cpuid(void) {
/* CPUID is an x86 specific interface. */
#if defined(__i386__) || defined(__x86_64__)
static const struct {
const char *cpuid;
int id;
} cpuid_vendor_table[] = {
{ "XenVMMXenVMM", VIRTUALIZATION_XEN },
{ "KVMKVMKVM", VIRTUALIZATION_KVM },
{ "TCGTCGTCGTCG", VIRTUALIZATION_QEMU },
/* http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1009458 */
{ "VMwareVMware", VIRTUALIZATION_VMWARE },
/* https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs */
{ "Microsoft Hv", VIRTUALIZATION_MICROSOFT },
/* https://wiki.freebsd.org/bhyve */
{ "bhyve bhyve ", VIRTUALIZATION_BHYVE },
{ "QNXQVMBSQG", VIRTUALIZATION_QNX },
};
uint32_t eax, ebx, ecx, edx;
bool hypervisor;
/* http://lwn.net/Articles/301888/ */
/* First detect whether there is a hypervisor */
if (__get_cpuid(1, &eax, &ebx, &ecx, &edx) == 0)
return VIRTUALIZATION_NONE;
hypervisor = !!(ecx & 0x80000000U);
if (hypervisor) {
union {
uint32_t sig32[3];
char text[13];
} sig = {};
unsigned j;
/* There is a hypervisor, see what it is */
__cpuid(0x40000000U, eax, ebx, ecx, edx);
sig.sig32[0] = ebx;
sig.sig32[1] = ecx;
sig.sig32[2] = edx;
log_debug("Virtualization found, CPUID=%s", sig.text);
for (j = 0; j < ELEMENTSOF(cpuid_vendor_table); j ++)
if (streq(sig.text, cpuid_vendor_table[j].cpuid))
return cpuid_vendor_table[j].id;
return VIRTUALIZATION_VM_OTHER;
}
#endif
log_debug("No virtualization found in CPUID");
return VIRTUALIZATION_NONE;
}
bool
sse42_enabled_cpu()
{
unsigned int ax, bx, cx, dx;
if (__get_cpuid(1, &ax, &bx, &cx, &dx) == 0)
return 0;
return (cx & (1 << 20)) != 0;
}
unsigned int
__libat_feat1_init (void)
{
unsigned int eax, ebx, ecx, edx;
FEAT1_REGISTER = 0;
__get_cpuid (1, &eax, &ebx, &ecx, &edx);
/* See the load in load_feat1. */
__atomic_store_n (&__libat_feat1, FEAT1_REGISTER, __ATOMIC_RELAXED);
return FEAT1_REGISTER;
}
static bool
have_sse2 (void)
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return false;
return (edx & bit_SSE2) != 0;
}
regs_t get_cpuid(unsigned int level) {
regs_t re = { 0 };
static_assert(sizeof(re) == (sizeof(uint32_t) * 4), "illegal size of struct regs_t ");
# if ( defined(__INTEL_COMPILER) || defined(_MSC_VER) )
__cpuid(reinterpret_cast<int*>(&re), static_cast<int>(level));
# elif defined(__GNUC__)
__get_cpuid(level, &re.EAX, &re.EBX, &re.ECX, &re.EDX);
# endif
return re;
}
// RDTSCP Instruction support (80000001H EDX Bit 27)
static
bool rdtscp_supported() {
uint32_t eax, ebx, ecx, edx;
if (!__get_cpuid(0x80000001, &eax, &ebx, &ecx, &edx)) {
return false;
}
return ((edx >> 27) & 1);
}
// Invariant TSC support (80000007H EDX Bit 08)
static
bool invariant_tsc() {
uint32_t eax, ebx, ecx, edx;
if (!__get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx)) {
return false;
}
return ((edx >> 8) & 1);
}
bool F2M_HardwareSupportsSIMD()
{
unsigned int CPUInfo[4];
#ifdef WIN32
__cpuid((int*)CPUInfo, 1);
#else
__get_cpuid(1, &CPUInfo[0], &CPUInfo[1], &CPUInfo[2], &CPUInfo[3]);
#endif
bool sse = ((CPUInfo[3] & (1 << 26)) != 0);
return sse;
}
static u32_t cpuid_extended_features(void)
{
u32_t eax, ebx, ecx = 0U, edx;
if (__get_cpuid(CPUID_EXTENDED_FEATURES_LVL,
&eax, &ebx, &ecx, &edx) == 0) {
return 0;
}
return edx;
}
static unsigned init_caps(void) {
unsigned int caps = 0;
unsigned int eax, ebx, ecx, edx;
if (__get_cpuid(1, &eax, &ebx, &ecx, &edx)) {
if (edx & (1 << 26)) {
caps |= CPU_CAP_SSE2;
}
if (ecx & (1 << 19)) {
caps |= CPU_CAP_SSE4_1;
}
}
if (__get_cpuid(7, &eax, &ebx, &ecx, &edx)) {
if (ebx & (1 << 5)) {
caps |= CPU_CAP_AVX2;
}
}
return caps;
}
int aesni_supported( void )
{
static uint32_t flags = 0xdeadbabe;
uint32_t regs[4];
if( flags == 0xdeadbabe )
{
__get_cpuid( 1, ®s[0], ®s[1], ®s[2], ®s[3] );
flags = regs[2];
}
return( flags & 0x2000000 );
}
static bool is_sse4_2_supported(void)
{
#if defined(__SSE42__) && (defined(__i386__) || defined(__x86_64__))
unsigned int eax, ebx, ecx, edx;
#ifdef __APPLE__
__get_cpuid(1, &eax, &ebx, &ecx, &edx);
#else
__cpuid(1, eax, ebx, ecx, edx);
#endif
return ecx & 0x00080000; // SSE4.2
#else
return false;
#endif
}
check_avx (void)
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
exit (0);
/* Run AVX test only if host has AVX support. */
if (((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE))
&& avx_os_support ())
return;
exit (0);
}
int s2n_cpu_supports_rdrand()
{
#if defined(__x86_64__)||defined(__i386__)
uint32_t eax, ebx, ecx, edx;
if (!__get_cpuid(1, &eax, &ebx, &ecx, &edx)) {
return 0;
}
if (ecx & RDRAND_ECX_FLAG) {
return 1;
}
#endif
return 0;
}
/**
* Checks the SSE2 feature bit returned by the CPUID instruction
* @return Does the CPU support SSE2?
*/
bool Zoom::haveSSE2()
{
#ifdef __GNUC__
unsigned int CPUInfo[4] = {0, 0, 0, 0};
__get_cpuid(1, CPUInfo, CPUInfo+1, CPUInfo+2, CPUInfo+3);
#elif _WIN32
int CPUInfo[4];
__cpuid(CPUInfo, 1);
#else
unsigned int CPUInfo[4] = {0, 0, 0, 0};
#endif
return (CPUInfo[3] & 0x04000000) ? true : false;
}
check_avx (void)
{
if (avx == -1)
{
unsigned int eax, ebx, ecx, edx;
if (__get_cpuid (1, &eax, &ebx, &ecx, &edx)
&& (ecx & bit_AVX))
avx = 1;
else
avx = 0;
}
return avx;
}
int
main ()
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run AVX vector test only if host has AVX support. */
if (ecx & bit_AVX)
vector_1_x ();
exit (0);
}
int
main (void)
{
#ifdef __x86_64__
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
if (!(ecx & bit_CMPXCHG16B))
return 0;
#endif
test ();
return 0;
}
int
main (void)
{
unsigned int eax, ebx, ecx, edx;
/* Run AVX test only if AVX is supported. */
if (__get_cpuid (1, &eax, &ebx, &ecx, &edx)
&& (ecx & bit_AVX))
{
__m256i ymm = _mm256_setzero_si256 ();
__m256i ret = audit_test (ymm, ymm, ymm, ymm, ymm, ymm, ymm, ymm);
ymm = _mm256_set1_epi32 (0x12349876);
if (memcmp (&ymm, &ret, sizeof (ret)))
abort ();
}
return 0;
}
// Constructor.
// Tests the architecture in a system-dependent way to detect AVX, SSE and
// any other available SIMD equipment.
SIMDDetect::SIMDDetect() {
#if defined(X86_BUILD)
# if defined(__linux__) || defined(__MINGW32__)
unsigned int eax, ebx, ecx, edx;
if (__get_cpuid(1, &eax, &ebx, &ecx, &edx) != 0) {
sse_available_ = (ecx & 0x00080000) != 0;
avx_available_ = (ecx & 0x10000000) != 0;
}
# elif defined(_WIN32)
int cpuInfo[4];
__cpuid(cpuInfo, 0);
if (cpuInfo[0] >= 1) {
__cpuid(cpuInfo, 1);
sse_available_ = (cpuInfo[2] & 0x00080000) != 0;
avx_available_ = (cpuInfo[2] & 0x10000000) != 0;
}
# endif
#endif // X86_BUILD
}
void
cpuid(
std::uint32_t id,
std::uint32_t& eax,
std::uint32_t& ebx,
std::uint32_t& ecx,
std::uint32_t& edx)
{
#ifdef BOOST_MSVC
int regs[4];
__cpuid(regs, id);
eax = regs[0];
ebx = regs[1];
ecx = regs[2];
edx = regs[3];
#else
__get_cpuid(id, &eax, &ebx, &ecx, &edx);
#endif
}
static void (*resolve_GOST34112012Final(void))(void)
{
uint32_t eax, ebx, ecx, edx;
if (__get_cpuid(1, &eax, &ebx, &ecx, &edx)) {
if (ecx & bit_SSE4_1) {
return (func_t)&GOST34112012Final_sse41;
}
if (edx & bit_SSE2) {
return (func_t)&GOST34112012Final_sse2;
}
if (edx & bit_MMX) {
return (func_t)&GOST34112012Final_mmx;
}
}
return (func_t)&GOST34112012Final_ref;
}
