static int alloc_pin(struct sunxi_hci_hcd *sunxi_ehci)
{
u32 ret = 1;
if(sunxi_ehci->drv_vbus_gpio_valid){
ret = gpio_request(sunxi_ehci->drv_vbus_gpio_set.gpio.gpio, NULL);
if(ret != 0){
DMSG_PANIC("ERR: gpio_request failed\n");
sunxi_ehci->drv_vbus_gpio_valid = 0;
}else{
gpio_direction_output(sunxi_ehci->drv_vbus_gpio_set.gpio.gpio, 0);
}
}
if(sunxi_ehci->usb_restrict_valid){
ret = gpio_request(sunxi_ehci->restrict_gpio_set.gpio.gpio, NULL);
if(ret != 0){
DMSG_PANIC("ERR: gpio_request failed\n");
sunxi_ehci->usb_restrict_valid = 0;
}else{
gpio_direction_output(sunxi_ehci->restrict_gpio_set.gpio.gpio, 0);
}
}
if(sunxi_ehci->usb_restrict_valid){
if(sunxi_ehci->usb_restrict_flag){
__gpio_set_value(sunxi_ehci->restrict_gpio_set.gpio.gpio, 0);
}else{
__gpio_set_value(sunxi_ehci->restrict_gpio_set.gpio.gpio, 1);
}
}
return 0;
}
/*
* This function must be defined to set the state of the WAKEUP pin
* on the WestBridge device. Generally this is done via a GPIO of
* some type.
*/
cy_bool cy_as_hal_set_wakeup_pin(cy_as_hal_device_tag tag, cy_bool state)
{
if(state) {
__gpio_set_value(AST_WAKEUP, 1);
} else {
__gpio_set_value(AST_WAKEUP, 0);
}
return cy_true;
}
static void __sunxi_set_vbus(struct sunxi_hci_hcd *sunxi_hci, int is_on)
{
u32 on_off = 0;
DMSG_INFO("[%s]: Set USB Power %s\n", sunxi_hci->hci_name, (is_on ? "ON" : "OFF"));
/* set power flag */
sunxi_hci->power_flag = is_on;
/* set power */
if(sunxi_hci->drv_vbus_gpio_set.gpio.data == 0){
on_off = is_on ? 1 : 0;
}else{
on_off = is_on ? 0 : 1;
}
if(sunxi_hci->drv_vbus_gpio_valid){
if((sunxi_hci->regulator_io != NULL) && (sunxi_hci->regulator_io_hdle != NULL)){
if(on_off){
if(regulator_enable(sunxi_hci->regulator_io_hdle) < 0){
DMSG_INFO("ERR: %s: regulator_enable fail\n", sunxi_hci->hci_name);
}
}else{
if(regulator_disable(sunxi_hci->regulator_io_hdle) < 0){
DMSG_INFO("ERR: %s: regulator_disable fail\n", sunxi_hci->hci_name);
}
}
}
__gpio_set_value(sunxi_hci->drv_vbus_gpio_set.gpio.gpio, on_off);
}
return;
}
void gpio_set_value(unsigned gpio, int value)
{
if (gpio < ath79_gpio_count)
__ath79_gpio_set_value(gpio, value);
else
__gpio_set_value(gpio, value);
}
__s32 OSAL_GPIO_DevWRITE_ONEPIN_DATA(u32 p_handler, __u32 value_to_gpio, const char *gpio_name)
{
if(p_handler) {
__gpio_set_value(p_handler, value_to_gpio);
} else {
__wrn("OSAL_GPIO_DevWRITE_ONEPIN_DATA, hdl is NULL\n");
}
return 0;
}
/**
* input_set_power_enable - input set power enable
* Input:
* type:
* enable:
* return value: 0 : success
* -EIO : i/o err.
*/
int input_set_power_enable(enum input_sensor_type *input_type, u32 enable)
{
int ret = -1;
struct regulator *ldo = NULL;
u32 power_io = 0;
void *data = NULL;
switch (*input_type) {
case CTP_TYPE:
data = container_of(input_type,
struct ctp_config_info, input_type);
ldo = ((struct ctp_config_info *)data)->ctp_power_ldo;
power_io = ((struct ctp_config_info *)data)->ctp_power_io.gpio;
break;
case GSENSOR_TYPE:
break;
case LS_TYPE:
break;
case IR_TYPE:
break;
default:
break;
}
if ((enable != 0) && (enable != 1)) {
return ret;
}
if(ldo) {
if(enable) {
regulator_enable(ldo);
} else {
if (regulator_is_enabled(ldo))
regulator_disable(ldo);
}
} else if(power_io) {
if(enable) {
__gpio_set_value(power_io,1);
} else {
__gpio_set_value(power_io,0);
}
}
return 0;
}
void gtp_set_int_value(int status)
{
int gpio_status = -1;
gpio_status = sw_gpio_getcfg(CTP_IRQ_NUMBER);
if(gpio_status != 1){
sw_gpio_setcfg(CTP_IRQ_NUMBER, 1);
}
__gpio_set_value(CTP_IRQ_NUMBER, status);
}
/*
*******************************************************************************
* pin_init
*
* Description:
* void
*
* Parameters:
* void
*
* Return value:
* void
*
* note:
* void
*
*******************************************************************************
*/
static int alloc_pin(struct sw_hci_hcd *sw_ehci)
{
u32 ret = 1;
if(sw_ehci->drv_vbus_gpio_valid){
ret = gpio_request(sw_ehci->drv_vbus_gpio_set.gpio.gpio, NULL);
if(ret != 0){
DMSG_PANIC("ERR: gpio_request failed\n");
sw_ehci->drv_vbus_gpio_valid = 0;
}else{
/* set config, ouput */
sw_gpio_setcfg(sw_ehci->drv_vbus_gpio_set.gpio.gpio, 1);
/* reserved is pull down */
sw_gpio_setpull(sw_ehci->drv_vbus_gpio_set.gpio.gpio, 2);
}
}
if(sw_ehci->usb_restrict_valid){
ret = gpio_request(sw_ehci->restrict_gpio_set.gpio.gpio, NULL);
if(ret != 0){
DMSG_PANIC("ERR: gpio_request failed\n");
sw_ehci->usb_restrict_valid = 0;
}else{
/* set config, ouput */
sw_gpio_setcfg(sw_ehci->restrict_gpio_set.gpio.gpio, 1);
/* reserved is pull down */
sw_gpio_setpull(sw_ehci->restrict_gpio_set.gpio.gpio, 2);
}
}
if(sw_ehci->usb_restrict_valid){
if(sw_ehci->usb_restrict_flag){
__gpio_set_value(sw_ehci->restrict_gpio_set.gpio.gpio, 0);
}else{
__gpio_set_value(sw_ehci->restrict_gpio_set.gpio.gpio, 1);
}
}
return 0;
}
static int __init ctp_init(void)
{
int err = -1;
if (ctp_fetch_sysconfig_para()) {
printk("%s: ctp_fetch_sysconfig_para err.\n", __func__);
return 0;
} else {
err = ctp_init_platform_resource();
if(0 != err) {
printk("%s:ctp_ops.init_platform_resource err. \n", __func__);
}
}
ctp_print_info(config_info,DEBUG_INIT);
msleep(10);
__gpio_set_value(config_info.irq_gpio_number, 1);
msleep(1);
__gpio_set_value(config_info.wakeup_gpio_number, 1);
return 0;
}
static int gpio_sw_data_set(struct gpio_sw_classdev *gpio_sw_cdev,int data)
{
struct gpio_sw *gpio = to_gpio(gpio_sw_cdev);
GPIO_SW_DEBUG("attending gpio_sw_data_set \n");
GPIO_SW_DEBUG("pio_hdle is %u \n",gpio->cdev.pio_hdle);
__gpio_set_value(gpio->cdev.pio_hdle, data);
gpio_sw_cdev->data=data;
GPIO_SW_DEBUG("left gpio_sw_data_set \n");
return 0;
}
int ctp_key_light(int status,int ms)
{
u32 gpio_status;
dprintk(DEBUG_INIT,"***CTP*** %s:status:%d,ms = %d\n",__func__,status,ms);
gpio_status = sw_gpio_getcfg(config_info.key_light_gpio_number);
if(gpio_status != 1) {
sw_gpio_setcfg(config_info.key_light_gpio_number,1);
}
if(status == 0) {
if(ms == 0) {
__gpio_set_value(config_info.key_light_gpio_number, 0);
} else {
__gpio_set_value(config_info.key_light_gpio_number, 0);
msleep(ms);
__gpio_set_value(config_info.key_light_gpio_number, 1);
}
}
if(status == 1) {
if(ms == 0) {
__gpio_set_value(config_info.key_light_gpio_number, 1);
} else {
__gpio_set_value(config_info.key_light_gpio_number, 1);
msleep(ms);
__gpio_set_value(config_info.key_light_gpio_number, 0);
}
}
msleep(10);
if(gpio_status != 1) {
sw_gpio_setcfg(config_info.key_light_gpio_number,gpio_status);
}
return 0;
}
/**
* ctp_wakeup - function
*
*/
int ctp_wakeup(int status,int ms)
{
dprintk(DEBUG_INIT,"***CTP*** %s:status:%d,ms = %d\n",__func__,status,ms);
if (status == 0) {
if(ms == 0) {
__gpio_set_value(config_info.wakeup_gpio.gpio, 0);
}else {
__gpio_set_value(config_info.wakeup_gpio.gpio, 0);
msleep(ms);
__gpio_set_value(config_info.wakeup_gpio.gpio, 1);
}
}
if (status == 1) {
if(ms == 0) {
__gpio_set_value(config_info.wakeup_gpio.gpio, 1);
}else {
__gpio_set_value(config_info.wakeup_gpio.gpio, 1);
msleep(ms);
__gpio_set_value(config_info.wakeup_gpio.gpio, 0);
}
}
msleep(5);
return 0;
}
int os_gpio_write(u32 p_handler, __u32 value_to_gpio, const char *gpio_name, int force_value_flag)
{
#ifdef VFE_GPIO
if(1 == force_value_flag)
{
if(p_handler)
{
__gpio_set_value(p_handler, value_to_gpio);
}
else
{
vfe_dbg(0,"os_gpio_write, hdl is NULL\n");
}
}
else
{
if(p_handler)
{
if(value_to_gpio == 0)
{
os_gpio_set_status(p_handler, 1, gpio_name);
__gpio_set_value(p_handler, value_to_gpio);
}
else
{
os_gpio_set_status(p_handler, 0, gpio_name);
}
}
else
{
vfe_dbg(0,"os_gpio_write, hdl is NULL\n");
}
}
#endif
return 0;
}
void gtp_set_int_value(int status)
{
long unsigned int config;
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC,0xFFFF);
pin_config_get(SUNXI_PINCTRL,irq_pin_name,&config);
if (1 != SUNXI_PINCFG_UNPACK_VALUE(config)){
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC,1);
pin_config_set(SUNXI_PINCTRL,irq_pin_name,config);;
}
__gpio_set_value(CTP_IRQ_NUMBER, status);
}
void gpio_set_value(unsigned gpio, int state)
{
u32 val;
u32 mask;
if (gpio >= STLS2F_N_GPIO) {
__gpio_set_value(gpio, state);
return ;
}
mask = 1 << gpio;
spin_lock(&gpio_lock);
val = LOONGSON_GPIODATA;
if (state)
val |= mask;
else
val &= (~mask);
LOONGSON_GPIODATA = val;
spin_unlock(&gpio_lock);
}
/*
*******************************************************************************
* __set_vbus
*
* Description:
* void
*
* Parameters:
* void
*
* Return value:
* void
*
* note:
* void
*
*******************************************************************************
*/
static void __set_vbus(struct sw_hci_hcd *sw_hci, int is_on)
{
u32 on_off = 0;
DMSG_INFO("[%s]: Set USB Power %s\n", sw_hci->hci_name, (is_on ? "ON" : "OFF"));
/* set power flag */
sw_hci->power_flag = is_on;
/* set power */
if(sw_hci->drv_vbus_gpio_set.gpio.data == 0){
on_off = is_on ? 1 : 0;
}else{
on_off = is_on ? 0 : 1;
}
if(sw_hci->drv_vbus_gpio_valid){
__gpio_set_value(sw_hci->drv_vbus_gpio_set.gpio.gpio, on_off);
}
printk("%s\n", __func__);
return;
}
static int sunxi_host_set_vbus(struct sunxi_otgc *otgc, int is_on)
{
DMSG_INFO("Set USB Power %s\n",(is_on ? "ON" : "OFF"));
if (otgc->port_ctl.drv_vbus.valid) {
if((otgc->port_ctl.regulator_io != NULL) && (otgc->port_ctl.regulator_io_hdle != NULL)){
if(is_on){
if(regulator_enable(otgc->port_ctl.regulator_io_hdle) < 0){
DMSG_INFO("ERR: usb0 regulator_enable fail\n");
}
}else{
if(regulator_disable(otgc->port_ctl.regulator_io_hdle) < 0){
DMSG_INFO("ERR: usb0 regulator_disable fail\n");
}
}
}
__gpio_set_value(otgc->port_ctl.drv_vbus.gpio_set.gpio.gpio, is_on);
}
return 0;
}
/**
* ctp_wakeup - function
*
*/
static int ctp_wakeup(struct gpio_config gpio, int ms)
{
int status = 0;
if(0 != gpio_request(gpio.gpio, NULL)) {
printk(KERN_ERR "wakeup gpio_request is failed\n");
return -1;
}
if (0 != gpio_direction_output(gpio.gpio, gpio.data)) {
printk(KERN_ERR "wakeup gpio set err!");
return -1;
}
printk("%s: !!!!gpio data %d\n", __func__, gpio.data);
if(!(gpio.data))
status = 1;
if(status == 0){
if(ms == 0) {
__gpio_set_value(gpio.gpio, 0);
}else {
__gpio_set_value(gpio.gpio, 0);
msleep(ms);
__gpio_set_value(gpio.gpio, 1);
}
}
if(status == 1){
if(ms == 0) {
__gpio_set_value(gpio.gpio, 1);
}else {
__gpio_set_value(gpio.gpio, 1);
msleep(ms);
__gpio_set_value(gpio.gpio, 0);
}
}
msleep(5);
gpio_free(gpio.gpio);
return 0;
}
/*
* initialize OMAP pads/pins to user defined functions
*/
static void cy_as_hal_init_user_pads(user_pad_cfg_t *pad_cfg_tab)
{
/*
* browse through the table an dinitiaze the pins
*/
u32 in_level = 0;
u16 tmp16, mux_val;
while (pad_cfg_tab->name != NULL) {
if (gpio_request(pad_cfg_tab->pin_num, NULL) == 0) {
pad_cfg_tab->valid = 1;
mux_val = omap_cfg_reg_L(pad_cfg_tab->mux_func);
/*
* always set drv level before changing out direction
*/
__gpio_set_value(pad_cfg_tab->pin_num,
pad_cfg_tab->drv);
/*
* "0" - OUT, "1", input omap_set_gpio_direction
* (pad_cfg_tab->pin_num, pad_cfg_tab->dir);
*/
if (pad_cfg_tab->dir)
gpio_direction_input(pad_cfg_tab->pin_num);
else
gpio_direction_output(pad_cfg_tab->pin_num,
pad_cfg_tab->drv);
/* sample the pin */
in_level = __gpio_get_value(pad_cfg_tab->pin_num);
cy_as_hal_print_message(KERN_INFO "configured %s to "
"OMAP pad_%d, DIR=%d "
"DOUT=%d, DIN=%d\n",
pad_cfg_tab->name,
pad_cfg_tab->pin_num,
pad_cfg_tab->dir,
pad_cfg_tab->drv,
in_level
);
} else {
/*
* get the pad_mux value to check on the pin_function
*/
cy_as_hal_print_message(KERN_INFO "couldn't cfg pin %d"
"for signal %s, its already taken\n",
pad_cfg_tab->pin_num,
pad_cfg_tab->name);
}
tmp16 = *(u16 *)PADCFG_VMA
(omap_mux_pin_cfg[pad_cfg_tab->mux_func].offset);
cy_as_hal_print_message(KERN_INFO "GPIO_%d(PAD_CFG=%x,OE=%d"
"DOUT=%d, DIN=%d IRQEN=%d)\n\n",
pad_cfg_tab->pin_num, tmp16,
OMAP_GPIO_BIT(pad_cfg_tab->pin_num, GPIO_OE),
OMAP_GPIO_BIT(pad_cfg_tab->pin_num, GPIO_DATA_OUT),
OMAP_GPIO_BIT(pad_cfg_tab->pin_num, GPIO_DATA_IN),
OMAP_GPIO_BIT(pad_cfg_tab->pin_num, GPIO_IRQENABLE1)
);
/*
* next pad_cfg deriptor
*/
pad_cfg_tab++;
}
cy_as_hal_print_message(KERN_INFO"pads configured\n");
}
static void e1735_suspend_dfll_bypass(void)
{
__gpio_set_value(TEGRA_GPIO_PS5, 1); /* tristate external PWM buffer */
}
/*
* init OMAP h/w resources
*/
int cy_as_hal_omap_cram_start(const char *pgm,
cy_as_hal_device_tag *tag, cy_bool debug)
{
cy_as_omap_dev_kernel *dev_p ;
int i;
u16 data16[4];
uint32_t err = 0;
/* No debug mode support through argument as of now */
(void)debug;
have_irq = false;
/*
* Initialize the HAL level endpoint DMA data.
*/
for (i = 0 ; i < sizeof(end_points)/sizeof(end_points[0]) ; i++) {
end_points[i].data_p = 0 ;
end_points[i].pending = cy_false ;
end_points[i].size = 0 ; /* No debug mode support through argument as of now */
(void)debug;
end_points[i].type = cy_as_hal_none ;
end_points[i].sg_list_enabled = cy_false;
/*
* by default the DMA transfers to/from the E_ps don't
* use sg_list that implies that the upper devices like
* blockdevice have to enable it for the E_ps in their
* initialization code
*/
}
/* allocate memory for OMAP HAL*/
dev_p = (cy_as_omap_dev_kernel *)cy_as_hal_alloc(
sizeof(cy_as_omap_dev_kernel)) ;
if (dev_p == 0) {
cy_as_hal_print_message("out of memory allocating OMAP"
"device structure\n") ;
return 0 ;
}
dev_p->m_sig = CY_AS_OMAP_CRAM_HAL_SIG;
/* initialize OMAP hardware and StartOMAPKernelall gpio pins */
err = cy_as_hal_processor_hw_init(dev_p);
if(err)
goto bus_acc_error;
/*
* Now perform a hard reset of the device to have
* the new settings take effect
*/
__gpio_set_value(AST_WAKEUP, 1);
/*
* do Astoria h/w reset
*/
DBGPRN(KERN_INFO"-_-_pulse -> westbridge RST pin\n");
/*
* NEGATIVE PULSE on RST pin
*/
__gpio_set_value(AST_RESET, 0);
mdelay(1);
__gpio_set_value(AST_RESET, 1);
mdelay(50);
/*
* NOTE: if you want to capture bus activity on the LA,
* don't use printks in between the activities you want to capture.
* prinks may take milliseconds, and the data of interest
* will fall outside the LA capture window/buffer
*/
cy_as_hal_dump_reg((cy_as_hal_device_tag)dev_p);
data16[0] = cy_as_hal_read_register((cy_as_hal_device_tag)dev_p, CY_AS_MEM_CM_WB_CFG_ID);
if ( (data16[0]&0xA100 != 0xA100) || (data16[0]&0xA200 != 0xA200)) {
/*
* astoria device is not found
*/
printk(KERN_ERR "ERROR: astoria device is not found, "
"CY_AS_MEM_CM_WB_CFG_ID %4.4x", data16[0]);
goto bus_acc_error;
}
cy_as_hal_print_message(KERN_INFO" register access test:"
"\n CY_AS_MEM_CM_WB_CFG_ID:%4.4x\n"
"after cfg_wr:%4.4x\n\n",
data16[0], data16[1]);
dev_p->thread_flag = 1 ;
spin_lock_init(&int_lock) ;
dev_p->m_next_p = m_omap_list_p ;
m_omap_list_p = dev_p ;
*tag = dev_p;
cy_as_hal_configure_interrupts((void *)dev_p);
cy_as_hal_print_message(KERN_INFO"OMAP3430__hal started tag:%p"
", kernel HZ:%d\n", dev_p, HZ);
/*
*make processor to storage endpoints SG assisted by default
*/
cy_as_hal_set_ep_dma_mode(4, true);
cy_as_hal_set_ep_dma_mode(8, true);
return 1 ;
/*
* there's been a NAND bus access error or
* astoria device is not connected
*/
bus_acc_error:
/*
* at this point hal tag hasn't been set yet
* so the device will not call omap_stop
*/
cy_as_hal_omap_hardware_deinit(dev_p);
cy_as_hal_free(dev_p) ;
return 0;
}
static void e1735_resume_dfll_bypass(void)
{
__gpio_set_value(TEGRA_GPIO_PS5, 0); /* enable PWM buffer operations */
}
static int exynos_fimc_is_sensor_pin_control(struct platform_device *pdev,
struct pinctrl *pinctrl, struct exynos_sensor_pin *pin_ctrls, int channel)
{
int ret = 0;
char ch_name[30];
int pin = pin_ctrls->pin;
int delay = pin_ctrls->delay;
char* name = pin_ctrls->name;
enum pin_act act = pin_ctrls->act;
int voltage = pin_ctrls->voltage;
struct pinctrl_state *s;
snprintf(ch_name, sizeof(ch_name), "%s%d", name, channel);
pr_info("%s(pin(%d), act(%d), ch(%s), delay(%d), voltage(%d))\n", __func__, pin, act, ch_name, delay, voltage);
switch (act) {
case PIN_PULL_NONE:
break;
case PIN_OUTPUT_HIGH:
if (gpio_is_valid(pin)) {
gpio_request_one(pin, GPIOF_OUT_INIT_HIGH, "CAM_GPIO_OUTPUT_HIGH");
usleep_range(delay, delay);
gpio_free(pin);
}
break;
case PIN_OUTPUT_LOW:
if (gpio_is_valid(pin)) {
gpio_request_one(pin, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW");
usleep_range(delay, delay);
gpio_free(pin);
}
break;
case PIN_INPUT:
if (gpio_is_valid(pin)) {
gpio_request_one(pin, GPIOF_IN, "CAM_GPIO_INPUT");
gpio_free(pin);
}
break;
case PIN_RESET:
if (gpio_is_valid(pin)) {
gpio_request_one(pin, GPIOF_OUT_INIT_HIGH, "CAM_GPIO_RESET");
usleep_range(1000, 1000);
__gpio_set_value(pin, 0);
usleep_range(1000, 1000);
__gpio_set_value(pin, 1);
usleep_range(1000, 1000);
gpio_free(pin);
}
break;
case PIN_FUNCTION:
s = (struct pinctrl_state *)pin_ctrls->pin;
ret = pinctrl_select_state(pinctrl, s);
if (ret < 0) {
pr_err("%s: cam %s, state %p pinctrl_select_statee is failed\n", __func__, ch_name, s);
return ret;
}
usleep_range(1000, 1000);
break;
case PIN_REGULATOR_ON:
{
struct regulator *regulator;
regulator = regulator_get(&pdev->dev, name);
if (IS_ERR_OR_NULL(regulator)) {
pr_err("%s : regulator_get(%s) fail\n", __func__, name);
return PTR_ERR(regulator);
}
if(voltage > 0) {
pr_info("%s : regulator_set_voltage(%d)\n",__func__, voltage);
ret = regulator_set_voltage(regulator, voltage, voltage);
if(ret) {
pr_err("%s : regulator_set_voltage(%d) fail\n", __func__, ret);
}
}
if (regulator_is_enabled(regulator)) {
pr_warning("%s regulator is already enabled\n", name);
regulator_put(regulator);
return 0;
}
ret = regulator_enable(regulator);
if (ret) {
pr_err("%s : regulator_enable(%s) fail\n", __func__, name);
regulator_put(regulator);
return ret;
}
usleep_range(delay, delay);
regulator_put(regulator);
}
break;
case PIN_REGULATOR_OFF:
{
struct regulator *regulator;
regulator = regulator_get(&pdev->dev, name);
if (IS_ERR_OR_NULL(regulator)) {
pr_err("%s : regulator_get(%s) fail\n", __func__, name);
return PTR_ERR(regulator);
}
if (!regulator_is_enabled(regulator)) {
pr_warning("%s regulator is already disabled\n", name);
regulator_put(regulator);
return 0;
}
ret = regulator_disable(regulator);
if (ret) {
pr_err("%s : regulator_disable(%s) fail\n", __func__, name);
regulator_put(regulator);
return ret;
}
usleep_range(delay, delay);
regulator_put(regulator);
}
break;
default:
pr_err("unknown act for pin\n");
break;
}
return ret;
}
/*
* Set output GPIO level
*/
void pxa_gpio_set_value(unsigned gpio, int value)
{
__gpio_set_value(gpio, value);
}
static int ltq_pci_startup(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const __be32 *req_mask, *bus_clk;
u32 temp_buffer;
/* get our clocks */
clk_pci = clk_get(&pdev->dev, NULL);
if (IS_ERR(clk_pci)) {
dev_err(&pdev->dev, "failed to get pci clock\n");
return PTR_ERR(clk_pci);
}
clk_external = clk_get(&pdev->dev, "external");
if (IS_ERR(clk_external)) {
clk_put(clk_pci);
dev_err(&pdev->dev, "failed to get external pci clock\n");
return PTR_ERR(clk_external);
}
/* read the bus speed that we want */
bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
if (bus_clk)
clk_set_rate(clk_pci, *bus_clk);
/* and enable the clocks */
clk_enable(clk_pci);
if (of_find_property(node, "lantiq,external-clock", NULL))
clk_enable(clk_external);
else
clk_disable(clk_external);
/* setup reset gpio used by pci */
reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
if (gpio_is_valid(reset_gpio)) {
int ret = devm_gpio_request(&pdev->dev,
reset_gpio, "pci-reset");
if (ret) {
dev_err(&pdev->dev,
"failed to request gpio %d\n", reset_gpio);
return ret;
}
gpio_direction_output(reset_gpio, 1);
}
/* enable auto-switching between PCI and EBU */
ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
/* busy, i.e. configuration is not done, PCI access has to be retried */
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
wmb();
/* BUS Master/IO/MEM access */
ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
/* enable external 2 PCI masters */
temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
/* setup the request mask */
req_mask = of_get_property(node, "req-mask", NULL);
if (req_mask)
temp_buffer &= ~((*req_mask & 0xf) << 16);
else
temp_buffer &= ~0xf0000;
/* enable internal arbiter */
temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
/* enable internal PCI master reqest */
temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
/* enable EBU request */
temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
/* enable all external masters request */
temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
wmb();
/* setup BAR memory regions */
ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
/* both TX and RX endian swap are enabled */
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
wmb();
ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
PCI_CR_BAR12MASK);
ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
PCI_CR_BAR13MASK);
/*use 8 dw burst length */
ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
wmb();
/* setup irq line */
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
/* toggle reset pin */
if (gpio_is_valid(reset_gpio)) {
__gpio_set_value(reset_gpio, 0);
wmb();
mdelay(1);
__gpio_set_value(reset_gpio, 1);
}
return 0;
}
/**
* ctp_detect - Device detection callback for automatic device creation
* return value:
* = 0; success;
* < 0; err
*/
static int ctp_detect(struct i2c_client *client, struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int ret;
u8 buf[8] = {GTP_REG_VERSION >> 8, GTP_REG_VERSION & 0xff};
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)){
pr_err("i2c_check_functionality err\n======return=====\n");
return -ENODEV;
}
if(twi_id == adapter->nr){
pr_debug("%s: addr= %x\n",__func__,client->addr);
msleep(50);
ret = gtp_i2c_read(client, buf, 6);
gtp_i2c_end_cmd(client);
if(buf[3] != 0x18)
{
pr_debug("%s:IC is not gt818\n",__func__);
return -ENODEV;
}
GTP_INFO("IC VERSION:%02x%02x_%02x%02x", buf[3], buf[2], buf[5], buf[4]);
strlcpy(info->type, CTP_NAME, I2C_NAME_SIZE);
//printk("%s:I2C connection might be something wrong ! \n",__func__);
return 0;
}else{
return -ENODEV;
}
}
/**
* ctp_print_info - sysconfig print function
* return value:
*
*/
static void ctp_print_info(struct ctp_config_info info,int debug_level)
{
if(debug_level == DEBUG_INIT)
{
dprintk(DEBUG_INIT,"info.ctp_used:%d\n",info.ctp_used);
dprintk(DEBUG_INIT,"info.twi_id:%d\n",info.twi_id);
dprintk(DEBUG_INIT,"info.screen_max_x:%d\n",info.screen_max_x);
dprintk(DEBUG_INIT,"info.screen_max_y:%d\n",info.screen_max_y);
dprintk(DEBUG_INIT,"info.revert_x_flag:%d\n",info.revert_x_flag);
dprintk(DEBUG_INIT,"info.revert_y_flag:%d\n",info.revert_y_flag);
dprintk(DEBUG_INIT,"info.exchange_x_y_flag:%d\n",info.exchange_x_y_flag);
dprintk(DEBUG_INIT,"info.irq_gpio_number:%d\n",info.irq_gpio.gpio);
dprintk(DEBUG_INIT,"info.wakeup_gpio_number:%d\n",info.wakeup_gpio.gpio);
}
}
/**
* ctp_wakeup - function
*
*/
static int ctp_wakeup(int status,int ms)
{
dprintk(DEBUG_INIT,"***CTP*** %s:status:%d,ms = %d\n",__func__,status,ms);
if (status == 0) {
if(ms == 0) {
__gpio_set_value(config_info.wakeup_gpio.gpio, 0);
}else {
__gpio_set_value(config_info.wakeup_gpio.gpio, 0);
msleep(ms);
__gpio_set_value(config_info.wakeup_gpio.gpio, 1);
}
}
if (status == 1) {
if(ms == 0) {
__gpio_set_value(config_info.wakeup_gpio.gpio, 1);
}else {
__gpio_set_value(config_info.wakeup_gpio.gpio, 1);
msleep(ms);
__gpio_set_value(config_info.wakeup_gpio.gpio, 0);
}
}
msleep(5);
return 0;
}
static int exynos_fimc_is_module_pin_control(struct platform_device *pdev,
struct pinctrl *pinctrl, struct exynos_sensor_pin *pin_ctrls)
{
char* name = pin_ctrls->name;
ulong pin = pin_ctrls->pin;
u32 delay = pin_ctrls->delay;
u32 value = pin_ctrls->value;
u32 voltage = pin_ctrls->voltage;
enum pin_act act = pin_ctrls->act;
int ret = 0;
switch (act) {
case PIN_NONE:
usleep_range(delay, delay);
break;
case PIN_OUTPUT:
if (gpio_is_valid(pin)) {
if (value)
gpio_request_one(pin, GPIOF_OUT_INIT_HIGH, "CAM_GPIO_OUTPUT_HIGH");
else
gpio_request_one(pin, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW");
usleep_range(delay, delay);
gpio_free(pin);
}
break;
case PIN_INPUT:
if (gpio_is_valid(pin)) {
gpio_request_one(pin, GPIOF_IN, "CAM_GPIO_INPUT");
gpio_free(pin);
}
break;
case PIN_RESET:
if (gpio_is_valid(pin)) {
gpio_request_one(pin, GPIOF_OUT_INIT_HIGH, "CAM_GPIO_RESET");
usleep_range(1000, 1000);
__gpio_set_value(pin, 0);
usleep_range(1000, 1000);
__gpio_set_value(pin, 1);
usleep_range(1000, 1000);
gpio_free(pin);
}
break;
case PIN_FUNCTION:
{
struct pinctrl_state *s = (struct pinctrl_state *)pin;
ret = pinctrl_select_state(pinctrl, s);
if (ret < 0) {
pr_err("pinctrl_select_state(%s) is fail(%d)\n", name, ret);
return ret;
}
}
break;
case PIN_REGULATOR:
{
struct regulator *regulator = NULL;
regulator = regulator_get(&pdev->dev, name);
if (IS_ERR_OR_NULL(regulator)) {
pr_err("%s : regulator_get(%s) fail\n", __func__, name);
return PTR_ERR(regulator);
}
if (value) {
if(voltage > 0) {
pr_info("%s : regulator_set_voltage(%d)\n",__func__, voltage);
ret = regulator_set_voltage(regulator, voltage, voltage);
if(ret) {
pr_err("%s : regulator_set_voltage(%d) fail\n", __func__, ret);
}
}
if (regulator_is_enabled(regulator)) {
pr_warning("%s regulator is already enabled\n", name);
regulator_put(regulator);
return 0;
}
ret = regulator_enable(regulator);
if (ret) {
pr_err("%s : regulator_enable(%s) fail\n", __func__, name);
regulator_put(regulator);
return ret;
}
} else {
if (!regulator_is_enabled(regulator)) {
pr_warning("%s regulator is already disabled\n", name);
regulator_put(regulator);
return 0;
}
ret = regulator_disable(regulator);
if (ret) {
pr_err("%s : regulator_disable(%s) fail\n", __func__, name);
regulator_put(regulator);
return ret;
}
}
usleep_range(delay, delay);
regulator_put(regulator);
}
break;
default:
pr_err("unknown act for pin\n");
break;
}
return ret;
}
/**
* set_host_status() - This function is used to write to Imx51 GPIO1_3.
*
* @value: The value of the host gpio either TRUE or FALSE.
*
* Return: None.
*/
void set_host_status (int value)
{
__gpio_set_value(RSI_GPIO_WRITE, value);
}
